
Inter-IC Bus
IIC Protocol
68HC(9)12DG128 Rev 1.0
MOTOROLA
Inter-IC Bus
257
7-iicbus
Clock
Synchronization
Since wire-AND logic is performed on SCL line, a high-to-low transition
on SCL line affects all the devices connected on the bus. The devices
start counting their low period and once a device's clock has gone low, it
holds the SCL line low until the clock high state is reached. However, the
change of low to high in this device clock may not change the state of the
SCL line if another device clock is still within its low period. Therefore,
synchronized clock SCL is held low by the device with the longest low
period. Devices with shorter low periods enter a high wait state during this
time (see
Figure 40
). When all devices concerned have counted off their
low period, the synchronized clock SCL line is released and pulled high.
There is then no difference between the device clocks and the state of the
SCL line and all the devices start counting their high periods. The first
device to complete its high period pulls the SCL line low again.
Figure 40 IIC Clock Synchronization
Handshaking
The clock synchronization mechanism can be used as a handshake in
data transfer. Slave devices may hold the SCL low after completion of
one byte transfer (9 bits). In such case, it halts the bus clock and forces
the master clock into wait states until the slave releases the SCL line.
SCL1
SCL2
SCL
Internal Counter Reset
WAIT
Start Counting High Period