參數(shù)資料
型號: 5P49EE502NDGI
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/26頁
文件大?。?/td> 0K
描述: IC CLOCK GENERATOR 20QFN
標準包裝: 100
系列: VersaClock™
類型: 時鐘發(fā)生器
PLL: 帶旁路
輸入: LVTTL,晶體
輸出: LVCMOS,LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 1:5
差分 - 輸入:輸出: 無/無
頻率 - 最大: 120MHz
除法器/乘法器: 是/無
電源電壓: 1.71 V ~ 1.89 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-VFQFN 裸露焊盤
供應商設備封裝: 20-VFQFPN(3x3)
包裝: 管件
其它名稱: 800-2522
DATASHEET
VERSACLOCK LOW POWER CLOCK GENERATOR
IDT5P49EE502
IDT VERSACLOCK LOW POWER CLOCK GENERATOR
1
IDT5P49EE502
REV L 072512
Description
The IDT5P49EE502 is a programmable clock generator
intended for low power, battery operated consumer
applications. There are four internal PLLs, each individually
programmable, allowing for up to five differrent output
frequencies. The frequencies are generated from a single
reference clock. The reference clock can come from either
a TCXO or fundamental mode crystal.
The IDT5P49EE502 can be programmed through the use
of the I2C interfaces. The programming interface enables
the device to be programmed when it is in normal operation
or what is commonly known as in system programmable.
An internal EEPROM allows the user to save and restore
the configuration of the device without having to reprogram
it on power-up.
Each of the four PLLs has an 8-bit reference divider and a
11-bit feedback divider. This allows the user to generate
four unique non-integer-related frequencies. The PLL loop
bandwidth is programmable to allow the user to tailor the
PLL response to the application. For instance, the user can
tune the PLL parameters to minimize jitter generation or to
maximize jitter attenuation. Spread spectrum generation is
supported on one of the PLLs.
Spread spectrum generation is supported on one of the
PLLs. The device is specifically designed to work with
display applications to ensure that the spread profile
remains consistent for each HSYNC in order to reduce
ROW noise. It also may operate in standard spread
spectrum mode.
There are total five 8-bit output dividers. The outputs are
connected to the PLLs via the switch matrix. The switch
matrix allows the user to route the PLL outputs to any
output bank. This feature can be used to simplify and
optimize the board layout. In addition, each output's slew
rate and enable/disable function can be programmed.
Target Applications
Smart Mobile Handset
Personal Navigation Device (PND)
Camcorder
DSC
Portable Game Console
Personal Media Player
Features
Four internal PLLs
Internal non-volatile EEPROM
Internal I2C EEPROM master interface
FAST (400kHz) mode I2C serial interfaces
Input Frequencies
– TCXO: 10 MHz to 40 MHz
– Crystal: 8 MHz to 30 MHz
Output Frequency Ranges: kHz to 120 MHz
Each PLL has an 8-bit reference divider and a 11-bit
feedback-divider
8-bit output-divider blocks
One of the PLLs support Spread Spectrum generation
capable of configuration to pixel rate, with adjustable
modulation rate and amplitude to support video clock
with no visible artifacts
I/O Standards:
– Outputs - 1.8V/2.5V/3.3 V LVTTL/ LVCMOS
2 independent adjustable VDDO groups.
Programmable Slew Rate Control
Programmable Loop Bandwidth Settings
Programmable output inversion to reduce bimodal jitter
Individual output enable/disable
Power-down/Sleep mode
– 10
μA max in power down mode
1.8V VDD Core Voltage
Available in 20pin 3x3mm QFN packages
-40 to +85 C Industrial Temp operation
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