參數(shù)資料
型號(hào)： 5962R0150202VYX
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 16 MHz, RISC PROCESSOR, QFP132
封裝： FP-132
文件頁(yè)數(shù)： 31/53頁(yè)
文件大?。?/td> 458K
代理商： 5962R0150202VYX
37
Literal
When the UT1750AR uses the Literal mode, the source operand
is a 5-bit literal data value. The UT1750AR explicitly states this
literal data value for the RISC instructions. The UT1750AR
encodes a 5-bit field, bits 4 through 0, in each instruction as
follows:
0 -- 00000
-16 -- 10000
+1 -- 00001
-15 -- 10001
+2 -- 00010
-14 -- 10010
+3 -- 00011
-13 -- 10011
+4 -- 00100
-12 -- 10100
+5 -- 00101
-11 -- 10101
+6 -- 00110
-10 -- 10110
+7 -- 00111
- 9 -- 10111
+8 -- 01000
- 8 -- 11000
+9 -- 01001
- 7 -- 11001
+10 -- 01010
- 6 -- 11010
+11 -- 01011
- 5 -- 11011
+12 -- 01100
- 4 -- 11100
+13 -- 01101
- 3 -- 11101
+14 -- 01110
- 2 -- 11110
+15 -- 01111
- 1 -- 11111
Immediate Long
When the UT1750AR uses the Immediate Long mode, the
source operand is a 16-bit data value. The UT1750AR explicitly
states this data for all RISC instructions and encodes the 16-bit
data in a second 16-bit instruction word (figure 32). The
UT1750AR encodes the 5-bit field of the instruction source
field, bits 4 through 0, as follows:
IMM -- 11111
Special Source Operand Addressing Modes
In addition to its three direct addressing modes, the UT1750AR
also supports three modes of indirect addressing: (1) Data
Register Indirect; (2) Stack Pointer Indirect; and (3) Absolute.
Data Register Indirect
When the UT1750AR uses the Data Register Indirect mode, the
source operand is a memory location addressed by the contents
of the specified data register. The data register is explicitly stated
for all RISC instructions. This mode is only available on the LR,
STR, INR, and STR instructions. The UT1750AR encodes a 5-
bit field, bits 4 through 0, in each instruction as follows:
R0 -- 00000
XR0 -- 10000
R1 -- 00001
R16 -- 10001
R2 -- 00010
XR2 -- 10010
R3 -- 00011
R17 -- 10011
R4 -- 00100
R5 -- 00101
XR16 -- 10101
R6 -- 00110
XR6 -- 10110
R7 -- 00111
R8 -- 01000
XR8 -- 11000
R9 -- 01001
R18 -- 11001
R10 -- 01010
XR10 -- 11010
R11 -- 01011
R19 -- 11011
R12 -- 01100
XR12 -- 11100
R13 -- 01101
XR18 -- 11101
R14 -- 01110
XR14 -- 11110
R15 -- 01111
Reserved -- 10111
and 11111
Stack Pointer Indirect
When the UT1750AR uses the Stack Pointer Indirect mode, the
source operand is a memory location addressed by the contents
of the Stack Pointer (SP) register. This mode is only available
with POP and PUSH instructions. The UT1750AR encodes a 5-
bit field, bits 11 through 15, of each instruction when in the
Stack Pointer Indirect mode as follows:
SP -- 10111.
Absolute
When the UT1750AR uses the Absolute mode, the source
operand is the memory location addressed by the contents of the
16-bit immediate-data field accompanying the instruction. This
mode is only available on the LR, STR, INR, and OTR
instructions. The system programmer encodes the immediate
data field as a second 16-bit instruction word.
Data Movement Operations
The UT1750AR places no restrictions on operand size during
data movement. This means the size (Byte, Word, or Long
Word) of the data in the source and destination do not have to
match. The UT1750AR handles the data movement for all RISC
instructions.
When a RISC instruction specifies a word destination, a 16-bit
result is always stored in the destination. If the RISC instruction
specifies a 5-bit literal source operand, then the UT1750AR
sign-extends this source data to produce a 16-bit operand. If the
RISC instruction specifies a word-length source operand, there
is no manipulation of the source data. If the RISC instruction
specifies a long-word source operand, the UT1750AR only
retains the least significant 16 bits of the result. The UT1750AR
truncates the most significant 16 bits of the result.
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