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參數(shù)資料
| 型號(hào)： | 5962R0150201VYC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 12 MHz, RISC PROCESSOR, CPGA144 |
| 封裝： | CERAMIC, PGA-144 |
| 文件頁數(shù)： | 21/55頁 |
| 文件大?。?/td> | 685K |
| 代理商： | 5962R0150201VYC |
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28
The UT1750AR de-asserts the Output Enable(RISC
Instruction) ( OE). This inhibits the RISC instruction from
placing any data on the RISC data bus.
The UT1750AR asserts the Write Enable (RISC
Instruction) (WE) so the UT1750AR can write to RISC
Instruction memory.
The data from the register selected in the STRI
instruction is valid on the RISC Data bus during time
period CK2.
LRI Instruction Bus Cycle Operation
During an LRI instruction, the UT1750AR moves the RISC
instruction data from the RISC instruction memory to the
UT1750AR. Figure 29 shows the timing diagram of the signal
relationships for the UT1750AR during an LRI Instruction Bus
Cycle Operation.
Just as with the STRI instruction, before the UT1750AR
executes the LRI instruction the system programmer must load
the UT1750AR’s Accumulator (ACC) with the RISC address
from which the data will be read. After the ACC is loaded with
the address information, LRI instruction execution can take
place.
Executing the LRI instruction begins when the falling edge of
OSCIN signals the start of time period CK1. At the beginning
of CK1, the data previously stored in the ACC becomes a valid
address on the RISC Address bus (RA0-RA20) and the STATE1
output becomes active indicating the UT1750AR is executing
a RISC instruction.
The data on the RISC Data bus is read into the UT1750AR
during time period CK2. The function of the remainder of the
bus cycle (time periods CK3 and CK4) is the same as for other
RISC instructions. STATE1 is high, indicating the next RISC
instruction is being fetched from memory and is ready for
execution during the next bus cycle.
Figure 28. STRI Instruction Typical Timing
DATA VALID
DATA VALID (RSn)
DATA VALID
ADDRESS VALID (IC)
ADDRESS VALID (ACC)
DATA
RISC
ADDRESS
RISC
WE
OSCIN
CK1
CK2
CK3
CK4
STATE1
OE
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