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STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-96712
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
D
SHEET
8
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics - Continued.
Limits 2/
Test
Symbol
Test conditions 1/
-55
°C ≤ T
C ≤ +125°C
unless otherwise specified
Device
type
VCC
Group A
subgroups
Min
Max
Unit
9
1.0
12.0
CL = 50 pF
RL = 500Ω
See figure 4
All
10, 11
1.0
14.0
tPHL
8/
M, D, P, L, R, F
3/
All
4.5 V
9
1.0
14.0
9
1.0
9.0
CL = 50 pF
RL = 500Ω
See figure 4
All
10, 11
1.0
11.0
Propagation delay
time, An to Yn
tPLH
8/
M, D, P, L, R, F
3/
All
4.5 V
9
1.0
11.0
ns
9
1.0
11.0
CL = 50 pF
RL = 500Ω
See figure 4
All
10, 11
1.0
12.0
Output transition
time
tTHL,
tTLH
8/
M, D, P, L, R, F
3/
All
4.5 V
9
1.0
12.0
ns
1/
Each input/output, as applicable, shall be tested at the specified temperature, for the specified limits, to the tests in table IA
herein. Output terminals not designated shall be high level logic, low level logic, or open, except for the ICC and ΔICC tests,
the output terminals shall be open. When performing the ICC and ΔICC tests, the current meter shall be placed in the circuit
such that all current flows through the meter.
2/
For negative and positive voltage and current values, the sign designates the potential difference in reference to GND and
the direction of current flow respectively; and the absolute value of the magnitude, not the sign, is relative to the minimum
and maximum limits, as applicable, listed herein.
3/
RHA devices supplied to this drawing have been characterized through all levels M, D, P, L, R, and F of irradiation.
However, this device is only tested at the 'F' level. Pre and Post irradiation values are identical unless otherwise
specified in table IA. When performing post irradiation electrical measurements for any RHA level, TA = +25°C.
4/
Force/Measure functions may be interchanged.
5/
This test may be performed either one input at a time (preferred method) or with all input pins simultaneously at
VIN = VCC - 2.1 V (alternate method). Classes Q and V shall use the preferred method. When the test is performed using
the alternate test method, the maximum limit is equal to the number of inputs at a high TTL input level times 1.0 mA; and the
preferred method and limits are guaranteed. For the preferred method, a minimum of one input shall be tested. All other
inputs shall be guaranteed, if not tested, to the limits specified in table IA herein.
6/
Power dissipation capacitance (CPD) determines both the power consumption (PD) and current consumption (IS). Where
PD = (CPD + CL) (VCC x VCC)f + (ICC x VCC) + (n x d x ΔICC x VCC)
IS = (CPD + CL) VCCf + ICC + (n x d x ΔICC)
f is the frequency of the input signal; n is the number of device inputs at TTL levels; and d is the duty cycle of the input
signal.
7/
The test vectors used to verify the truth table shall, at a minimum, test all functions of each input and output. All possible
input to output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2 herein. For VOUT
measurements, L
≤ 0.5 V and H ≥ 4.0 V.
8/
AC limits at VCC = 5.5 V are equal to the limits at VCC = 4.5 V. For propagation delay tests, all paths must be tested.