- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄97783 > 5962-9174301M2A (NATIONAL SEMICONDUCTOR CORP) OP-AMP, 1600 uV OFFSET-MAX, CQCC20 PDF資料下載
參數(shù)資料
| 型號(hào)： | 5962-9174301M2A |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運(yùn)算放大器 |
| 英文描述： | OP-AMP, 1600 uV OFFSET-MAX, CQCC20 |
| 封裝： | LCC-20 |
| 文件頁(yè)數(shù)： | 13/14頁(yè) |
| 文件大?。?/td> | 373K |
| 代理商： | 5962-9174301M2A |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)當(dāng)前第13頁(yè)第14頁(yè)
Application Division (Continued)
Clamp Operation
The maximum positive or negative excursion of the output
voltage is determined by voltages applied to the clamping
pins, V
H and VL.VH determines the positive clamping level;
V
L determines the negative level. For example, if VH is set at
+2V and V
L is set at 0.5V the output voltage is restricted
within this 0.5V to +2V range. When the output voltage tries
to exceed this level, the amplifier goes into “clamp mode”
and the output voltage limits at the clamp voltage.
Clamp Accuracy and Amplifier Linearity
Ideally, the clamped output voltage and the clamp voltage
should be identical. In practice, however, there are two
sources of clamp inaccuracy: the inherent clamp accuracy
(which is shown in the specification page) and resistor di-
vider action of open-loop output resistance of 10
and the
load resistor. Or, in equation form,
(1)
When settling the clamp voltages, the designer should also
recognize that within about 200mV of the clamp voltages,
amplifier linearity begins to deteriorate. (See plot on previous
page.)
Biasing V
H and VL
Each of the clamping pins is buffered internally so simple
resistive voltage divider circuits work well in providing the
clamp voltages. V
L and VH can be set by choosing the
divider resistors using:
(2)
As a general guideline, let R
1 +R2 R3 +R4 5k.
V
H should be biased more positively than VL.VH may be
biased below 0V; however, with this biasing, the output
voltage will actually clamp at 0V unless a simple pull down
circuit is added to the op amp output (when clamped against
V
H, the output cannot sink current). An analogous situation
and design solution exists for V
L when it is biased above 0V,
but in this case, a pull up circuit is used to source current
when the amplifier is clamped against V
L.
The clamp voltage range rating is that for normal operation.
Problems in over driven linearity may occur if the clamps are
set outside this range so this is not suggested under any
conditions. If the clamping capability is not required, the
CLC402 (low gain op amp with fast 14-bit settling) may be a
more appropriate part.
The clamps, which have a bandwidth of about 50MHz, may
be driven by high frequency signal source. This allows the
clamping level to be modulated, which is useful in many
applications such as pulse amplitude modulation. The
source resistance of the signal source should be less than
500
to ensure stability.
Clamp-Mode Dynamics
As can be seen in the clamped pulse response plot, clamp-
ing is virtually instantaneous. Note, however, that there can
be a small amount of overshoot, as indicated on the speci-
fication page. The output voltage stays at the clamp voltage
level as long as the product of the input voltage and the gain
setting exceeds the clamp voltage. When the input voltage
decreases, it will eventually reach a point where it is no
longer trying to drive the output voltage above the clamp
voltage. When this occurs, there is typically a 5-10ns “over-
load recovery from clamp,” which is the time it takes for the
op amp to resume linear operation. The normal op amp
parameters, such as the rise time, apply when the op amp is
in linear operation.
Optimizing Settling Time Performance
To obtain the best possible settling time performance for the
CLC502, some additional design criteria must be consid-
ered, particularly when driving loads of less than 500
.
When driving a 100
load, a step of a few volts on the output
will create a large step of current in the power supplies. In
some cases, this step will cause a small ringing on the power
supply due to the bypass capacitor (.1F) oscillating with the
inductance in the power supply trace. The critical trace is the
power supply trace between the two capacitors (a trace
inductance of 20nH will be enough to degrade settling time
performance). The frequency of the ring can be determined
by
(3)
and any reduction in this frequency will improve performance
due to better power supply rejection at lower frequencies . To
obtain the best performance, small resistor, R
Q, may be
added in the trace to dampen the circuit (See
Figure 3). An
R
Q of 5-10 will result in excellent settling performance and
will have only minor impact on other performance character-
istics. No provision for R
Q has been made on the evaluation
board available from National as part #730013. It can, how-
ever, be easily added by cutting a trace and adding a 5- 10
resistor, as shown in
Figure 3, for both supplies.
DC Accuracy and Notes
Since the two inputs for the CLC502 are quite dissimilar, the
noise and offset error performance differs somewhat from
that of a standard differential input amplifier. The two input
bias currents are physically unrelated rendering bias current
cancellation
through
matching
of
the
inverting
and
non-inverting source resistance ineffective.
In Equation 3, the output offset is the algebraic sum of the
equivalent input voltage and current sources that influence
DC operation. Output noise is determine similarly except that
a root-sum-of-squares replaces the algebraic sum. R
s is the
non-inverting pin source resistance.
Output Offset V
o = ± IBNxRs (1+Rf/Rg) ±
VIO (1+ R
f /Rg) ± IBIxRf
Printed Circuit Layout
As with any high frequency device, a good PCB layout will
enhance performance. Ground plane construction and good
power supply bypassing close to the package are critical to
achieving full performance. In the non-inverting configura-
tion, the amplifier is sensitive to stray capacitance to ground
at the inverting input. Hence, the inverting node connections
should be small with minimal coupling to the ground plane.
Shunt capacitance across the feedback resistor should not
be used to compensate for this effect.
The device is also very sensitive to parasitic capacitance on
the output pin. The plots include a suggested series R
S to
de-couple this effect. Evaluation boards (part number
730013 for through-hole and 730027 for SOIC) for the
CLC502 are available.
CLC502
www.national.com
8
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 5962-9175801MXA | OP-AMP, 3500 uV OFFSET-MAX, 300 MHz BAND WIDTH, CDSO8 |
| 5962-9175802M2A | OP-AMP, 1800 uV OFFSET-MAX, CQCC20 |
| 5962-9300401MEX | QUAD OP-AMP, 6000 uV OFFSET-MAX, CDIP16 |
| 5962-9300401MEA | QUAD OP-AMP, 6000 uV OFFSET-MAX, CDIP16 |
| 5962-9313301MPX | OP-AMP, 80 uV OFFSET-MAX, 110 MHz BAND WIDTH, CDIP8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 5962-9174401MXA | 制造商:QP Semiconductor 功能描述:EPROM UV 256K-Bit 32K x 8 50ns 28-Pin CDIP |
| 5962-9174402MXA | 制造商:Cypress Semiconductor 功能描述:EPROM UV 256K-Bit 32K x 8 20ns 28-Pin CDIP 制造商:QP Semiconductor 功能描述:EPROM UV 256K-Bit 32K x 8 40ns 28-Pin CDIP |
| 5962-9174402MXX | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| 5962-9174601Q3A | 制造商:Texas Instruments 功能描述: |
| 5962-9174601QLA | 制造商:Texas Instruments 功能描述:Scan Buffer/Line Driver 8-CH Inverting 3-ST BiCMOS 24-Pin CDIP Tube |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。