- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄97783 > 5962-9099301MPA (NATIONAL SEMICONDUCTOR CORP) OP-AMP, 8000 uV OFFSET-MAX, 220 MHz BAND WIDTH, CDIP8 PDF資料下載
參數(shù)資料
| 型號： | 5962-9099301MPA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運算放大器 |
| 英文描述： | OP-AMP, 8000 uV OFFSET-MAX, 220 MHz BAND WIDTH, CDIP8 |
| 封裝： | CERDIP-8 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 519K |
| 代理商： | 5962-9099301MPA |
Application Information (Continued)
Slew Rate
The rapid turn on and off ability of the CLC505 is not recom-
mended for signal isolation applications (such as multiplex-
ing). While the power dissipation of the amplifier drops in the
off state, the amplifier may still have some gain at low
frequencies. Causing feed through in multiplex application.
The performance desired is that given for I
CC = 3.4mA under
standard conditions. From the I
CC vs. Ip plot, Ip=84A. Is
obtained now calculating R
p:
Slew rate limiting is a nonlinear response which occurs in
amplifiers when the output voltage swing cannot change as
rapidly as the applied input signal. The CLC505 has been
designed to avoid slew rate limiting in most circuit configu-
rations. The large signal (5V
PP) bandwidth of 80MHz at ICC =
3.4mA, is only slightly less than the 100MHz small signal
bandwidth. The result is a low distortion, linear system for
both small and large signals over the required system fre-
quency range.
The CLC505 reaches slew rate limits only for small
non-inverting gains. In other words, slew rate limiting is
constrained by common mode voltage swings at the input.
The large signal frequency response plot at a gain of +2 was
a break in the response, which indicates that a slew rate limit
has been reached. Note also that the frequency response
plots at a gain of +21 for large and small signal responses
are nearly identical.
Differential Gain and Phase
Differential gain and phase are measurements useful prima-
rily in composite video channels. They are measured by
monitoring the gain and phase changes of a high frequency
carrier (3.58MHz typically) as the output of the amplifier is
swept over a range of DC voltages.
Specifications for the CLC505 include differential gain and
phase. Test signals based on a 1V
PP video level. Test con-
ditions used are the following:
DC sweep range: 0 to 100 IRE units (black to white)
Carrier: 3.58MHz at 40 IRE units peak to peak
The amplifier conditions are significantly different for the
three values of supply current specified. At I
CC = 9mA, the
amplifier is specified for a gain of +2 and 150
load (for a
backmatched 75
system). IRE amplitudes at I
CC = 9mA,
are referred to the 75
load resistor.
At I
CC = 1mA and ICC = 3.4mA, the CLC505 is less capable
of driving a 150
load due to output current limitations. For
this reason lighter loads are used and the termination resis-
tor is omitted. The gain and load resistance for I
CC = 3.4mA
are A
V = +6 and RL = 500 and for ICC = 1mA; AV = +6 and
R
L =1k.
Source Impedance
For best results, source impedance in the non-inverting cir-
cuit configuration (see
Figure 1) should be kept below 5k
.
Above 5k
it is possible for oscillation to occur, depending
on other circuit board parasitics. For high signal source
impedances, a resistor with a value of less than 5k
may be
used to terminate the non-inverting input to ground.
Feedback Resistor
In current-feedback op amps, the value of the feedback
resistor plays a major role in determining amplifier dynamics.
It is important to select the correct value. The CLC505
provides optimum performance with a 1k
feedback resistor.
Selection of an incorrect value can lead to severe rolloff in
frequency response, (if the resistor value is too large) or
peaking or oscillation, (if the value is too low.)
Printed Circuit Layout
As with any high frequency device, a good PCB layout will
enhance performance. Ground plane construction and good
power supply bypassing close to the package are critical to
achieving full performance. In the non-inverting configura-
tion, the amplifier is sensitive to stray capacitance to ground
at the inverting input. Hence, the inverting node connections
should be small with minimal coupling to the ground plane.
Shunt capacitance across the feedback resistor should not
be used to compensate for this effect.
Precision buffed resistors (PRP8351 series from Precision
Resistive Products) with low parasitic reactances were used
to develop the data sheet specifications. Precision carbon
composition resistors will also yield excellent results. Stan-
dard spirally-trimmed RN55D metal film resistors will work
with a slight decrease in bandwidth due to their reactive
nature at high frequencies.
Evaluation PC boards (part number 730013 for through-hole
and 730027 for SOIC) for the CLC505 are available.
CLC505
www.national.com
14
相關PDF資料 |
PDF描述 |
|---|---|
| 5962-9153201QPA | DUAL COMPARATOR, 5000 uV OFFSET-MAX, CDIP8 |
| 5962-9153202QHA | DUAL COMPARATOR, 10000 uV OFFSET-MAX, CDFP10 |
| 5962-9153301M2X | BUTTERWORTH, LOWPASS, DIP |
| 5962-9153301MRX | DUAL SWITCHED CAPACITOR FILTER, RESISTOR PROGRAMMABLE, UNIVERSAL, CDIP20 |
| 5962-9153301M2A | ACTIVE FILTER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 5962-9099703MRA | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| 5962-9150101MZC | 制造商:e2v Technologies 功能描述:MCU 32-Bit 68000 RISC ROMLess 5V 132-Pin CPGA |
| 5962-9150102MXA | 制造商:e2v Aerospace & Defense 功能描述:MCU 32-Bit 6800 RISC ROMLess 5V 132-Pin CQUAD |
| 5962-9150801MXA | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Async Dual 5V 128K-Bit 16K x 8 70ns 68-Pin CPGA Tray 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 5V 128KBIT 16KX8 70NS 68PIN PGA - Rail/Tube |
| 5962-9150802MXA | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Async Dual 5V 128K-Bit 16K x 8 70ns 68-Pin CPGA Tray 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 5V 128KBIT 16KX8 70NS 68PIN PGA - Rail/Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復。