參數(shù)資料
型號(hào)： 5962-9099301MPA
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 運(yùn)算放大器
英文描述： OP-AMP, 8000 uV OFFSET-MAX, 220 MHz BAND WIDTH, CDIP8
封裝： CERDIP-8
文件頁(yè)數(shù)： 5/20頁(yè)
文件大?。?/td> 519K
代理商： 5962-9099301MPA
Application Information (Continued)
Selecting an Operating Point
The operating point is determined by the supply current,
which in turn is determined by current (I
p) flowing out of pin
8. As the supply current is reduced the following effects will
be observed:
Specification
Effect as I
CC
Decreases
Bandwidth
Decreases
Rise TIme
increases
Output Drive
Decreases
Input Bias Current
Decreases
Input Impedance
Increases (see
source impedance
discussion)
Both the specification pages and the plot pages illustrate
these effects to help make the supply current vs. perfor-
mance tradeoff. Performance is specified and tested at I
CC
=1mA, 3.4mA, and 9mA as indicated in the datasheet. (Note
some test conditions and especially the load resistance are
different for the three supply current settlings.) The perfor-
mance plots show typical performance for all three supply
currents levels.
When making the supply current vs. performance tradeoff, it
is first a good idea to see if one of the standard operating
points (I
CC = 9mA, 3.4mA, or 1mA) fits the application. If it
does, performance guaranteed on the specification pages
will apply directly to your application. In addition, the value of
R
p may be obtained directly from the specification page.
The following discussion will assist in selecting I
CC for
applications that cannot operate at one of the specified
supply current settlings.
Use the typical performance plots for critical specifications to
select the best I
CC. Now interpolate between the values of
I
CC
in the plots & specification tables to estimate the
max/min values in the application.
From the selected value of I
CC the “programming current”
(I
p) may be easily calculated:
I
P=ICC/39
The plot of I
CC vs Ip in the plot pages shows this relationship
graphically. Knowing I
p leads to a direct calculation of Rp.
R
p= [(+VPP1.6)Vn]/ Ip
R
p=8.4/Ip (for +VCC=+5V and Vn =5V)
V
n is the voltage externally applied to Rp. (Throughout the
data sheet and in most applications, V
n and VCC are 5V.)
The term (+V
CC1.6V) is the voltage at pin 8.
Now standard V
CC,VEE and Rp does not have to be con-
nected to V
CC. In applications where non-standard supply
voltages are used or when there is a need to power down the
op amp via digital logic control. The value of R
p is adjusted
accordingly.
First, an operating point needs to be determined from the
plots & specifications as discussed above. From this, I
p is
obtained. I
p, in concert with the available Vn determines Rp.
Example
An application requires that V
CC = ±3V and performance in
the 1mA operating point range. The required I
p can therefore
be determined as follows:
I
p=26A
R
p is connected from pin 8 to VCC and VCC=+/3V. Now
calculate R
p under new conditions:
R
p=[(+VCC1.6V)(VCC)]/Ip
R
p=[(+3V1.6V)(3V)]/26A
R
p=169k
The CLC505 will have performance similar to R
p = 300k
shown on the datasheet, but with 40% less power dissipation
due to the reduced supply voltages. (The op amp will also
have a more restricted common-mode range and output
swing.) This calculation is approximate and a prudent design
would include substantial performance margin for max/min
limits.
Dynamic Shutdown Capability
The CLC505 may be powered on and off very quickly by
controlling the voltage applied to R
p.IfRp is connected
between pin 8 and the output of a CMOS gate powered from
±5V supplies, the gate can be used to turn the amplifier on
and off. This is shown in
Figure 3 below:
When the gate output is switched from high to low, the
CLC505 will turn on. In the off state, the supply current
typically reduces to 0.2mA or less. The speed with which the
CLC505 turns on or off is limited by the capacitance at pin 8.
To improve switching time, a speed up capacitor from the
gate output to pin 8 is recommended. The value of this
capacitor will depend on the total capacitance connected to
pin 8 and is best established experimentally. Turn-on and
turn-off times of 100ns to 200ns are achievable with ordinary
CMOS gates.
Example:
An open collector logic device is used to dynamically control
the power dissipation of the circuit. Here, the desired con-
nection for R
p is from pin 8 to the open collector logic device.
When the logic gate goes low, the CLC505 is turned on.
Performance desired is that given for I
CC = 3.4mA under
standard conditions. From the I
CC vs. Ip plot, Ip = 84A. Then
calculating R
p:
R
p=[(+VCC1.6V)(V n)]/Ip
R
p=[(+5V1.6V)(0)]84A
R
p=40k
DS012755-49
FIGURE 3. Dynamic Control of Power Consumption
DS012755-50
FIGURE 4. Controlling Power on State with TTL Logic
CLC505
www.national.com
13
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