參數(shù)資料
型號(hào): 5962-8987705JA
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Buffer和線驅(qū)動(dòng)
英文描述: TRIPLE LINE TRANSCEIVER, CDIP24
封裝: 0.300 INCH, CERDIP-24
文件頁(yè)數(shù): 5/15頁(yè)
文件大?。?/td> 1575K
代理商: 5962-8987705JA
13
Maxim Integrated
40Mbps, +3.3V, RS-485 Half-Duplex
Transceivers
MAX14840E/MAX14841E
How-Swap Input Circuitry
The MAX14840E/MAX14841E DE and RE enable inputs
feature hot-swap capability. At the input, there are two
nMOS devices, M1 and M2 (Figure 10). When VCC
ramps from 0V, an internal 15Fs timer turns on M2 and
sets the SR latch that also turns on M1. Transistors M2
(a 1mA current sink) and M1 (a 100FA current sink) pull
DE to GND through a 5.6kI resistor. M2 is designed to
pull DE to the disabled state against an external parasitic
capacitance up to 100pF that can drive DE high. After
15s, the timer deactivates M2 while M1 remains on,
holding DE low against three-state leakages that can
drive DE high. M1 remains on until an external source
overcomes the required input current. At this time, the
SR latch resets and M1 turns off. When M1 turns off,
DE reverts to a standard, high-impedance CMOS input.
Whenever VCC drops below 1V, the hot-swap input is
reset.
For RE, there is a complementary circuit employing two
pMOS devices pulling RE to VCC.
±35kV ESD Protection
ESD protection structures are incorporated on all pins
to protect against electrostatic discharges encountered
during handling and assembly. The driver outputs and
receiver inputs of the MAX14840E family of devices have
extra protection against static electricity. The ESD struc-
tures withstand high ESD in all states: normal operation,
shutdown, and powered down. After an ESD event, the
MAX14840E/MAX14841E keep working without latchup
or damage.
ESD protection can be tested in various ways. The trans-
mitter outputs and receiver inputs of the MAX14840E/
MAX14841E are characterized for protection to the fol-
lowing limits:
Q35kV HBM
Q20kV using the Air Gap Discharge method specified
in IEC 61000-4-2
Q12kV using the Contact Discharge method specified
in IEC 61000-4-2
Figure 10. Simplified Structure of the Driver Enable Pin (DE)
VCC
TIMER
DE
TIMER
5.6kI
15Fs
100FA
1mA
M2
M1
DRIVER
ENABLE
(HOT SWAP)
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