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參數(shù)資料
| 型號(hào)： | 571MLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 571 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, SOIC-8 |
| 文件頁(yè)數(shù)： | 5/7頁(yè) |
| 文件大?。?/td> | 179K |
| 代理商： | 571MLF |
ICS571
LOW PHASE NOISE ZERO DELAY BUFFER
ZDB AND MULTIPLIER/DIVIDER
IDT / ICS LOW PHASE NOISE ZERO DELAY BUFFER
5
ICS571
REV H 051310
AC Electrical Characteristics
Unless stated otherwise, VDD = 5.0 V or 3.3 V, Ambient Temperature 0 to +70
° C
Notes:
1. Sresses beyond these can permanently damage the device.
2. Assumes clocks with the same rise time, measured from rising edges at VDD/2. Measured with 33
termination
resistors and 15 pF loads. Applies to both 3.3 V and 5 V operation.
3. CLK/2 has lower jitter (both absolute and one sigma, in ps) than CLK.
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency, clock input
fIN
FB from CLK
20
160
MHz
Input Frequency, clock input
fIN
FB from CLK/2
10
80
MHz
Skew CLK/2 with respect to CLK
Note 2
150
500
850
ps
Input clock to output connected to FBIN
Note 2
-500
500
ps
Output Clock Rise Time, 5 V
0.8 to 2.0 V, 15 pF load
0.3
ns
Output Clock Fall Time, 5 V
2.0 to 0.8 V, 15 pF load
0.4
ns
Output Clock Rise Time, 3.3 V
0.8 to 2.0 V, 15 pF load
0.45
ns
Output Clock Fall Time, 3.3 V
2.0 to 0.8 V, 15 pF load
0.55
ns
Input Clock Duty Cycle, 3.3 V
fin = 150 MHz
20
80
%
Output Clock Duty Cycle, 3.3 V
At VDD/2
45
49 to 51
55
%
Absolute Clock Period Jitter, CLK,
Note 3
Deviation from Mean
±80
ps
One-Sigma Clock Period Jitter, CLK,
Note 3
50
ps
Phase Noise, Relative to carrier
1 kHz offset
-105
dBc/Hz
Phase Noise, Relative to carrier
100 kHz offset
-115
dBc/Hz
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Thermal Resistance Junction to
Ambient
θJA
Still air
° C/W
θJA
1 m/s air flow
° C/W
θJA
3 m/s air flow
° C/W
Thermal Resistance Junction to Case
θJC
° C/W
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