參數(shù)資料
型號(hào)： 554AJ000398DG
廠商： SILICON LABORATORIES
元件分類： VCXO, clock
英文描述： VCXO, CLOCK, LVPECL OUTPUT
封裝： ROHS COMPLIANT PACKAGE-8
文件頁數(shù)： 8/14頁
文件大?。?/td> 238K
代理商： 554AJ000398DG
Si554
Rev. 0.6
3
Table 3. CLK± Output Frequency Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Nominal Frequency1,2,3
fO
LVDS/CML/LVPECL
10
—
945
MHz
CMOS
10
—
160
Temperature Stability1,4
TA = –40 to +85 °C
–20
–50
–100
—
+20
+50
+100
ppm
Absolute Pull Range1,4
APR
±25
—
±375
ppm
Aging
Frequency drift over first year.
—
±3
ppm
Frequency drift over 15 year life.
—
±10
Power up Time5
tOSC
——
10
ms
Settling Time After FS[1:0]
Change
tFRQ
Both FS[1] and FS[0] changing
simultaneously
——
20
ms
Notes:
1. See Section 3. "Ordering Information" on page 8 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Nominal output frequency set by VCNOM =VDD/2.
4. Selectable parameter specified by part number.
5. Time from power up or tristate mode to fO (to within ±1 ppm of fO).
Table 4. CLK± Output Levels and Symmetry
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
LVPECL Output Option1
VO
mid-level
VDD – 1.42
—
VDD – 1.25
V
VOD
swing (diff)
1.1
—
1.9
VPP
VSE
swing (single-ended)
0.55
—
0.95
VPP
LVDS Output Option2
VO
mid-level
1.125
1.20
1.275
V
VOD
swing (diff)
0.5
0.7
0.9
VPP
CML Output Option2
VO
mid-level
—
VDD – 0.75
—
V
VOD
swing (diff)
0.70
0.95
1.20
VPP
CMOS Output Option3
VOH
IOH =32mA
0.8 x VDD
—
VDD
V
VOL
IOL =32mA
—
0.4
Rise/Fall time (20/80%)
tR, tF
LVPECL/LVDS/CML
—
350
ps
CMOS with CL =15pF
—
1
—
ns
Symmetry (duty cycle)
SYM
LVPECL:
VDD – 1.3 V (diff)
LVDS:
1.25 V (diff)
CMOS:
VDD/2
45
—
55
%
Notes:
1. 50
to VDD – 2.0 V.
2. Rterm = 100 (differential).
3. CL = 15 pF
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