參數(shù)資料
型號(hào): 554AJ000398DG
廠商: SILICON LABORATORIES
元件分類: VCXO, clock
英文描述: VCXO, CLOCK, LVPECL OUTPUT
封裝: ROHS COMPLIANT PACKAGE-8
文件頁(yè)數(shù): 12/14頁(yè)
文件大小: 238K
代理商: 554AJ000398DG
Si554
Rev. 0.6
7
2. Pin Descriptions
Table 10. Si554 Pin Descriptions
Pin
Name
Type
Function
1
VC
Analog Input
Control Voltage
2
OE*
Input
Output Enable (Polarity = High):
0 = clock output disabled (outputs tri-stated)
1 = clock output enabled
3
GND
Ground
Electrical and Case Ground
4
CLK+
Output
Oscillator Output
5
CLK–
(N/A for CMOS)
Output
Complementary Output
(N/C for CMOS)
6
VDD
Power
Power Supply Voltage
7
FS[1]*
Input
Frequency Select MSB
8
FS[0]*
Input
Frequency Select LSB
*Note: FS[1:0] and OE include a 17 k
pullup resistor to VDD. Output Enable polarity selectable at time of order. See Section
3. "Ordering Information" on page 8 for details on frequency select and OE polarity ordering options.
(Top View)
1
2
3
6
5
4
VC
GND
OE
VDD
CLK+
CLK–
FS[1]
FS[0]
8
7
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