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參數(shù)資料
| 型號(hào)： | 4280 |
| 英文描述： | Low-Cost, 2.7V to 5.5V Temperature Switches in a SOT23 |
| 中文描述： | 4280組數(shù)據(jù)表數(shù)據(jù)表630K/JUN.11.99 |
| 文件頁數(shù)： | 5/48頁 |
| 文件大小： | 630K |
| 代理商： | 4280 |
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4
MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
CONNECTIONS OF UNUSED PINS
Pin
D
0
–D
7
E
0
, E
1
Set the output latch to “1” and open, or
connect to V
DD
pin (Note 2).
Open or connect to V
SS
pin.
Set the output latch to “0” and open, or
connect to V
SS
pin.
Notes 1: Port D
7
: Set the bit 2 (PU0
2
) of the pull-down control register PU0 to “0” by software and turn the pull-down transistor OFF.
2: Set the corresponding bits (PU0
0
, PU0
1
) of the pull-down control register PU0 to “0” by software and turn the pull-down
transistor OFF.
E
2
G
0
–G
3
Connection
Open or connect to V
DD
pin (Note 1).
(Note in order to set the output latch to “0” to make pins open)
After system is released from reset, a port is in a high-impedance state until the output latch of the port is set to “0” by software.
Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur.
To set the output latch periodically is recommended because the value of output latch may change by noise or a program run away
(caused by noise).
(Note when connecting to V
SS
and V
DD
)
Connect the unused pins to V
SS
or V
DD
at the shortest distance and use the thick wire against noise.
PORT FUNCTION
Control
bits
1 bit
Output:
2 bits
Input:
3 bits
4 bits
1 bit
Control
instructions
SD
RD
CLD
SD
RD
CLD
SZD
OEA
IAE
IAE
OGA
IAG
OCRA
Control
registers
PU0
PU0
C
Output structure
P-channel open-drain
P-channel open-drain
P-channel open-drain
CMOS
Input/
Output
Output
(7)
I/O
(1)
I/O
(2)
Input
(1)
I/O
(4)
Output
(1)
Remark
Pull-down function and key-on
wakeup function
(programmable)
Pull-down function and key-on
wakeup function
(programmable)
Pull-down function and key-on
wakeup function
Pin
D
0
–D
6
D
7
E
0
E
1
E
2
G
0
–G
3
CARR
Port
Port D
Port E
Port G
Port CARR
DEFINITION OF CLOCK AND CYCLE
System clock (STCK)
The system clock is the source clock for controlling this product.
It can be selected as shown below whether to use the CCK
instruction.
CCK instruction
When not using
When using
Instruction clock
f(X
IN
)/32
f(X
IN
)/4
System clock
f(X
IN
)/8
f(X
IN
)
Instruction clock (INSTCK)
The instruction clock is a signal derived by dividing the system
clock by 4, and is the basic clock for controlling CPU. The one
instruction clock cycle is equivalent to one machine cycle.
Machine cycle
The machine cycle is the cycle required to execute the
instruction.
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