參數(shù)資料
型號: 4014B
元件分類: 復位半導體
英文描述: 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit
中文描述: (142.54十一)
文件頁數(shù): 1/6頁
文件大?。?/td> 142K
代理商: 4014B
TL/F/5947
C
February 1988
CD4014BM/CD4014BC 8-Stage Static Shift Register
General Description
The CD4014BM/CD4014BC is an 8-stage parallel input/se-
rial output shift register. A parallel/serial control input en-
ables individual JAM inputs to each of 8 stages. Q outputs
are available from the sixth, seventh and eighth stages. All
outputs have equal source and sink current capabilities and
conform to standard ‘‘B’’ series output drive.
When the parallel/serial control input is in the logical ‘‘0’’
state, data is serially shifted into the register synchronously
with the positive transition of the clock. When the parallel/
serial control input is in the logical ‘‘1’’ state, data is jammed
into each stage of the register synchronously with the posi-
tive transition of the clock.
All inputs are protected against static discharge with diodes
to V
DD
and V
SS
.
Features
Y
Wide supply voltage range
3.0V to 15V
0.45 V
DD
(typ.)
Y
High noise immunity
Y
Low power TTL
compatibility
Fan out of 2 driving 74L
or 1 driving 74LS
Y
5V–10V–15V parametric ratings
Y
Symmetrical output characteristics
Y
Maximum input leakage:
1
m
A at 15V over full temperature range
Connection Diagram
Dual-In-Line Package
TL/F/5947–1
Top View
Truth Table
SerialPSerial
CL
*
Input
Control
PI 1 PI n(InQ1
Q
n
L
L
L
L
L
L
K
X
X
X
X
0
1
X
1
1
1
1
0
0
X
0
1
0
1
X
X
X
0
0
1
1
X
X
X
0
1
0
1
0
1
0
0
1
1
Q
n
b
1
Q
n
b
1
Q
n
Q1
No Change
*
Level change
X
e
Don’t care case
Order Number CD4014B
Logic Diagram
TL/F/5947–2
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
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