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參數(shù)資料
| 型號： | 28F004BX-T |
| 英文描述： | Quad Network Power Controller for Power-Over-LAN |
| 中文描述： | 4兆位（256 × 16。為512k × 8）啟動塊閃存系列 |
| 文件頁數(shù)： | 38/44頁 |
| 文件大?。?/td> | 496K |
| 代理商： | 28F004BX-T |
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28F400BL-T/B, 28F004BL-T/B
AC CHARACTERISTICS FOR WE
Y
-CONTROLLED WRITE OPERATIONS
(1)
V
CC
e
3.15V–3.6V, 5.0V
g
10%
Versions
(4)
28F400BL-150
28F004BL-150
Unit
Symbol
Parameter
Notes
Min
Max
t
AVAV
t
WC
Write Cycle Time
150
ns
t
PHWL
t
PS
RP
Y
High Recovery
to WE
Y
Going Low
1.0
m
s
t
ELWL
t
CS
CE
Y
Setup to WE
Y
Going Low
0
ns
t
PHHWH
t
PHS
RP
Y
V
HH
Setup to WE
Y
Going High
6, 8
200
ns
t
VPWH
t
VPS
V
PP
Setup to WE
Y
Going High
Address Setup to WE
Y
Going High
5, 8
200
ns
t
AVWH
t
AS
3
95
ns
t
DVWH
t
DS
Data Setup to WE
Y
Going High
4
100
ns
t
WLWH
t
WP
WE
Y
Pulse Width
100
ns
t
WHDX
t
DH
Data Hold from WE
Y
High
WE
Y
High
4
0
ns
t
WHAX
t
AH
Address Hold from WE
Y
High
3
10
ns
t
WHEH
t
CH
CE
Y
Hold from WE
Y
High
10
ns
t
WHWL
t
WPH
WE
Y
Pulse Width High
50
ns
t
WHQV1
Duration of Word/Byte
Programming Operation
2, 5, 6
6
m
s
t
WHQV2
Duration of Erase
Operation (Boot)
2, 5, 6
0.3
s
t
WHQV3
Duration of Erase
Operation (Parameter)
2, 5, 6
0.3
s
t
WHQV4
Duration of Erase
Operation (Main)
2, 5, 6
0.6
s
t
QVVL
t
VPH
V
PP
Hold from Valid SRD
RP
Y
V
HH
Hold from Valid SRD
5, 8
0
ns
t
QVPH
t
PHH
6, 8
0
ns
t
PHBR
Boot-Block Relock Delay
7, 8
200
ns
t
IR
Input Rise Time
10
ns
t
IF
Input Fall Time
10
ns
NOTES:
1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
Characteristics during Read Mode.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled inter-
nally which includes verify and margining operations.
3. Refer to command definition table for valid A
IN
.
4. Refer to command definition table for valid D
IN
.
5. Program/Erase durations are measured to valid SRD data (successful operation, SR.7
e
1).
6. For Boot Block Program/Erase, PWD
Y
should be held at V
HH
until operation completes successfully.
7. Time t
PHBR
is required for successful relocking of the Boot Block.
8. Sampled but not 100% tested.
38
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| 28F200BL-B | 2-MBIT (128K x 16. 256K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 28F004S3 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:BYTE-WIDE SMART 3 FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT |
| 28F004S5 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:BYTE-WIDE SMART 5 FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT |
| 28F004SC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT |
| 28F008B3 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:SMART 3 ADVANCED BOOT BLOCK BYTE-WIDE |
| 28F008BE-T/B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-MBIT (512K X 16. 1024K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
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