參數(shù)資料
型號： 1894-40KLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 網(wǎng)絡接口
英文描述： DATACOM, INTERFACE CIRCUIT, QCC40
封裝： 6 X 6 MM, ROHS COMPLIANT, QFN-40
文件頁數(shù)： 23/52頁
文件大?。?/td> 459K
代理商： 1894-40KLFT
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
IDT / ICS 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 3
ICS1894-40
REV C 092909
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
AMDIX
IN/Ipu
AMDIX Enable
2
TP_AP
AIO
Twisted pair port A (for either transmit or receive) positive signal
3
TP_AN
AIO
Twisted pair port A (for either transmit or receive) negative signal
4
VSS
Ground Connect to ground.
5
VDD
Power
3.3V Power Supply
6
TP_BN
AIO
Twisted pair port B (for either transmit or receive) negative signal
7
TP_BP
AIO
Twisted pair port B (for either transmit or receive) positive signal
8
VDD
Power
3.3V Power Supply
9
TCSR
AIO
Transmit Current bias pin, connected to Vdd and ground via two resistors.
10
VSS
Ground Connect to ground.
11
RESET_N
Input
Hardware reset for the whole chip (active low)
12
P2/INT
IO/Ipd
PHY address Bit 2 as input (during power on reset and hardware reset)
Interrupt output as output (default active low, can be programmed to active high)
13
MDIO
IO
Management Data Input/Output
14
MDC
Input
Management Data Clock
15
VDDIO
Power
3.3 V IO Power Supply.
16
HWSW/
CRS
IO/Ipu
Hard pin select enable as input (during power on reset and hardware reset) and
MII CRS as output
17
Regpin/
COL
IO/Ipd
Full register access enable as input (during power on reset and hardware reset) and
MII COL output
18
AMDIX/RXD3
IO/Ipu
AMDIX enable as input (during power on reset and hardware reset)
Receive data Bit 3 for MII
19
P3/RXD2
IO/Ipd
PHY address Bit 3 as input (during power on reset and hardware reset)
Receive data Bit 2 for MII as output.
20
RXTRI/
RXD1
IO/Ipu
RX isolate enable (during power on reset and hardware reset)
Received data Bit 1 for both RMII and MII
21
SI/LED4
IO/Ipd
MII/SI mode select as input (during power on reset and hardware reset) and
LED # 4 as output
22
FDPX/
RXD0
IO/Ipu
Full duplex enable (during power on reset and hardware reset)
Received data Bit 0 for both RMII and MII
23
RMII/RXDV
IO/Ipd
RMII/MII select as input (during power on reset and hardware reset)
Receive data valid for MII and CRS_DV for RMII as output
24
SPEED
Ipd
10/100M input select. 1 = 100M mode, 0 = 10M mode.
25
TXER
IN
TXER Input
26
ANSEL/
RXCLK9
IO/Ipu
Auto-negotiation enable(during power on reset and hardware reset)
Receive clock MII
27
NOD/
RXER
IO/Ipd
Node/repeater select (during power on reset and hardware reset)
Receive error
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