參數(shù)資料
型號： 0W344-004-XTP
廠商： ON SEMICONDUCTOR
元件分類： 數(shù)字信號處理
英文描述： BelaSigna 200 - Single-Chip Audio Processing System; Package: 52 PIN QFN 8x8; No of Pins: 52; Container: Tape and Reel; Qty per Container: 500
中文描述： 0-BIT, 33 MHz, MIXED DSP, QCC52
封裝： 8 X 8 MM, QFN-52
文件頁數(shù)： 4/43頁
文件大?。?/td> 1426K
代理商： 0W344-004-XTP
BelaSigna 200
4.2.2. CSP Pad Out
Table 4: Pad Out (Advance Information)
Pad
Index
Pad Name
Pad Function
I/O
U/D
B2
CAP0
Charge pump capacitor pin 0
N/A
A2
CAP1
Charge pump capacitor pin 1
N/A
A1
VDBL
Double voltage
O
N/A
C3
VREG
Regulated voltage for microphone bias
O
N/A
B3
A|0
Audio signal input to ADC0
I
N/A
B1
A|1/LOUT
Audio signal input to ADC0/line level output signal from preamp 0
I/O
N/A
C2
A|2
Audio signal input to ADC1
I
N/A
C1
A|3
Audio signal input to ADC1
I
N/A
B4
A|R
Reference voltage for microphone
N/A
C4
AGND
Analog ground
N/A
D1
AOR
Reference voltage for DAC
N/A
E1
AO1/RCVR1-
Audio signal output from DAC1/output from direct digital drive 1-
O
N/A
D2
AO0/RCVR1+
Audio signal output from DAC0/output from direct digital drive 1+
O
N/A
D3
RCVR0-
Output from direct digital drive 0
O
N/A
E3
RCVR0+
Output from direct digital drive 0
O
N/A
D4
RCVRGND
Receiver return current
N/A
E2
VBAT
Positive power supply
I
N/A
E5
VDD
Core logic, EEPROM and pad supply
I
N/A
A6
GNDO
Digital pads ground
N/A
E6
GNDC
Core logic and pads ground
N/A
D6
EXT_CLK
External clock input/internal clock output
I/O
U
E7
DEBUG_RX
Debug port receive
I
U
D7
DEBUG_TX
Debut port transmit
O
U
E8
TWSS_SDA
TWSS data
I/O
U
D8
TWSS_CLK
TWSS clock
I
U
C8
SPI_SERO
Serial peripheral interface serial data out
I/O
D
C7
SPI_SERI
Serial peripheral interface serial data in
I
U
B8
SPI_CS
Serial peripheral interface chip select
I/O
D
C6
SPI_CLK
Serial peripheral interface clock
I/O
N/A
A8
GPIO[14]/PCM_FRAME
General-purpose I/O/PCM interface frame
I/O
U
B7
GPIO[13]/PCM_OUT
General-purpose I/O/PCM interface output
I/O
U
A7
GPIO[12]/PCM_IN
General-purpose I/O/PCM interface input
I/O
U
B6
GPIO[11]/PCM_CLK
General-purpose I/O/PCM interface clock
I/O
U
A5
GPIO[10]/DCLK
General-purpose I/O/class D receiver clock
I/O
U
B5
LSAD[5]/GPIO[9]/UART_RX
Low-speed A/D/general-purpose I/O/general-purpose UART receive
I/O
U
A4
LSAD[4]/GPIO[8]/UART_TX
Low-speed A/D input/general-purpose I/O/general-purpose UART
transmit
I/O
U
C5
LSAD[3]/GPIO[7]
Low-speed A/D input/general purpose I/P
I/O
U
A3
LSAD[1]/GPIO[5]/I2S_OUT
A
Low-speed A/D inputs/general-purpose I/O/I2S interface analog
blocks output
I/O
U
D5
LSAD[0]/GPIO[4]/I2S_OUT
D
Low-speed A/D inputs/general-purpose I/O/I2S interface analog
blocks output
I/O
U
E4
GPIO[3]/
NCLK_DIV_RESET/I2S_FA
General-purpose I/O/clock divider reset/I2S interface analog blocks
frame output
I/O
U
Rev. 16 | Page 12 of 43 | www.onsemi.com
相關(guān)PDF資料
PDF描述
0W344-005-XTP BelaSigna 200 - Single-Chip Audio Processing System; Package: 52 PIN QFN 8x8; No of Pins: 52; Container: Tape and Reel; Qty per Container: 1000
0W588-002-XUA BelaSigna 200 - Single-Chip Audio Processing System; Package: WLCSP 40, 3.8x2.3; No of Pins: 40; Container: Tape and Reel; Qty per Container: 5000
0W633-001-XTP BelaSigna 250 - 16 bit Audio Processor, Full Stereo 2-in, 2-out; Package: LFBGA 57, 5x5; No of Pins: 57; Container: Tape and Reel; Qty per Container: 5000
0W888-002-XTP BelaSigna 250 - 16 bit Audio Processor, Full Stereo 2-in, 2-out; Package: LFBGA 64, 7x7; No of Pins: 64; Container: Tape and Reel; Qty per Container: 1500
0X860 OSCILLOSCOPE 100MHz ANALOGUE
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