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參數(shù)資料
| 型號： | 0W344-004-XTP |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | BelaSigna 200 - Single-Chip Audio Processing System; Package: 52 PIN QFN 8x8; No of Pins: 52; Container: Tape and Reel; Qty per Container: 500 |
| 中文描述： | 0-BIT, 33 MHz, MIXED DSP, QCC52 |
| 封裝： | 8 X 8 MM, QFN-52 |
| 文件頁數(shù)： | 39/43頁 |
| 文件大?。?/td> | 1426K |
| 代理商： | 0W344-004-XTP |
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BelaSigna 200
digital pads of BelaSigna 200 itself. Analog ground returns associated with the audio output stage should connect back to the star point
on separate individual traces.
For more information on the recommended ground design strategy, see Table 1.
In some designs, space constraints may make separate ground planes impractical. In this case a star configuration strategy should be
used. Each analog ground return should connect to the star point with separate traces.
3.2 Internal Power Supplies
Power management circuitry in BelaSigna 200 generates separate digital (VDDC) and analog (VREG, VDBL) regulated supplies. Each
supply requires an external decoupling capacitor, even if the supply is not used externally. Decoupling capacitors should be placed as
close as possible to the power pads. Further details are provided in Table 1. Non-critical signals are outlined in Table 2.
Table 1: Critical Signal
Pin Name
Description
Routing Guideline
VBAT
Power supply
Place 1μF (min) decoupling capacitor close to pin. Connect negative
terminal of capacitor to DGND plane.
VREG, VDBL
Internal regulator for analog
sections
Place separate 1μF decoupling capacitors close to each pin. Connect
negative capacitor terminal to AGND. Keep away from digital traces and
output traces. VREG may be used to generate microphone bias. VDBL
shall not be used to supply external circuitry.
AGND
Analog ground return
Connect to AGND plane.
VDDC
Internal regulator for digital
sections
Place 10μF decoupling capacitor close to pin. Connect negative terminal
of capacitor to DGND. Should be connected to VDDO pins and to
EEPROM power.
GNDO, GNDC
Digital ground return (pads and
core)
Connect to digital ground.
AI0, AI1 / LOUT, AI2, AI3
Microphone inputs
Keep as short as possible. Keep away from all digital traces and audio
outputs. Avoid routing in parallel with other traces. Connect unused inputs
to AGND.
AIR
Input stage reference voltage
Connect to AGND. If no analog ground plane, should share trace with
microphone grounds to star point.
AO0, AO1
Analog audio output
Keep away from microphone inputs.
RCVR0+, RCVR0-, RCVR1+,
RCVR1-
Direct digital audio output
Keep away from analog traces, particularly microphone inputs.
Corresponding traces should be of approximately the same length.
AOR
Output stage reference voltage
Connect to star point. Share trace with power amplifier (if present).
RCVRGND
Output stage ground return
Connect to star point.
EXT_CLK
External clock input / internal
clock output
Minimize trace length. Keep away from analog signals. If possible,
surround with digital ground.
AI_RC
Infrared receiver input
If used, minimize trace length to photodiode.
Rev. 16 | Page 5 of 43 | www.onsemi.com
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相關代理商/技術參數(shù) |
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| 0W344-005-XTP | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC BELASIGNA 200 QFN 1000RL RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
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| 0W589-007-XDS | 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC AUDIO AD/DA RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風格: 封裝 / 箱體: 封裝: |
| 0W598001EVK | 制造商:ON Semiconductor 功能描述:B250 EDK SGL PURCH - Bulk |
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