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| 型號(hào)： | μPD78F9418 |
| 廠商： | NEC Corp. |
| 英文描述： | 8 Bit Single Chip Microcontrollers(8位單片微控制器) |
| 中文描述： | 8位單片機(jī)微控制器（8位單片微控制器） |
| 文件頁(yè)數(shù)： | 53/128頁(yè) |
| 文件大?。?/td> | 614K |
| 代理商： | ΜPD78F9418 |
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53
μ
PD78F9418
(2) Watchdog timer mode register (WDTM)
The WDTM specifies the watchdog timer operation mode and whether to enable or disable counting.
The WDTM is set using a 1-bit or 8-bit memory manipulation instruction.
A RESET input clears the WDTM to 00H.
Figure 6-24. Watchdog Timer Mode Register Format
RUN
0
1
Watchdog timer operation selection
Note 1
RUN
0
0
WDTM4 WDTM3
0
0
0
WDTM
Symbol
Address
When reset
R/W
FFF9H
00H
R/W
6
7
5
4
3
2
1
0
Stops counting.
Clears the counter and causes it start.
WDTM4
0
0
1
1
Watchdog timer operation mode selection
Note 2
WDTM3
0
1
0
1
Operation disabled
Internal timer mode (When an overflow occurs, a maskable interrupt is issued.)
Note 3
Watchdog timer mode 1 (When an overflow occurs, a nonmaskable interrupt is issued.)
Watchdog timer mode 2 (When an overflow occurs, a reset operation is started.)
Notes 1.
Once the RUN bit has been set (1), it is impossible to zero-clear it by software. So, once counting
begins, it cannot be stopped by any means other than a RESET input.
2.
Once WDTM3 and WDTM4 have been set (1), it is impossible to zero-clear them by software.
3.
The interval timer starts operating when the RUN bit is set to 1.
Cautions 1. If the RUN bit is set to 1, and the watchdog timer is cleared, the actual overflow time
becomes 0.8 % (maximum) less than the time specified in timer clock selection register 2.
2. To use watchdog timer mode 1 or 2, ensure that the interrupt request flag (TMIF4) is set to
0, before setting WDTM4 to 1. If TMIF4 is set to 1, selecting mode 1 or 2 causes a
nonmaskable interrupt to be issued at the instant rewriting ends.
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