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15
LIST OF FIGURES (2/4)
Figure No.
Title
Page
6-1.
6-2.
6-3.
6-4.
6-5.
6-6.
6-7.
Block Diagram of 16-Bit Timer Counter........................................................................................... 101
Format of Timer 40 Control Register ............................................................................................... 102
Settings of Timer 40 Control Register at Interval Timer Operation.................................................. 103
Operating Timing of 16-Bit Timer Counter Used as Interval Timer.................................................. 104
Settings of Timer 40 Control Register at Free-Running Timer Operation........................................ 104
Operating Timing of 16-Bit Timer Counter Used as Free-Running Timer........................................ 105
Start Timing of 16-Bit Timer Register 40.......................................................................................... 106
7-1.
7-2.
7-3.
7-4.
7-5.
Block Diagram of 8-Bit Timer Counter............................................................................................. 108
8-Bit Timer Mode Control Register 00 Format................................................................................. 109
Settings of 8-Bit Timer Mode Control Register 00 in Interval Timer Operation................................ 110
Operating Timing of 8-Bit Timer Counter 00 Used as Interval Timer............................................... 111
Start Timing of 8-Bit Timer Register 00............................................................................................ 112
8-1.
8-2.
8-3.
Block Diagram of Watch Timer........................................................................................................ 113
Format of Watch Timer Mode Control Register ............................................................................... 115
Watch Timer/Interval Timer Operation Timing................................................................................. 117
9-1.
9-2.
9-3.
Block Diagram of Watchdog Timer.................................................................................................. 120
Format of Timer Clock Selection Register 2.................................................................................... 121
Format of Watchdog Timer Mode Register...................................................................................... 122
10-1.
10-2.
10-3.
10-4.
10-5.
10-6.
Block Diagram of Clock Output Circuit............................................................................................. 126
Format of PCL/BUZ Control Register 0 ........................................................................................... 127
Format of Port Mode Register 2....................................................................................................... 128
Setting of PCL/BUZ Control Register 0 for PCL Output Operation.................................................. 129
PCL Output Timing .......................................................................................................................... 129
Setting of PCL/BUZ Control Register 0 for Buzzer Output Operation.............................................. 130
11-1.
11-2.
11-3.
11-4.
11-5.
11-6.
11-7.
11-8.
11-9.
Block Diagram of Serial Interface .................................................................................................... 131
Format of Asynchronous Serial Interface Mode Register 00........................................................... 134
Format of Asynchronous Serial Interface Status Register 00.......................................................... 135
Format of Baud Rate Generator Control Register 00 ...................................................................... 136
Permissible Error in Baud Rate with Sampling Error Considered (where k = 0).............................. 143
Asynchronous Serial Interface Transmission/Reception Data Format ............................................ 144
Asynchronous Serial Interface Transmission Completion Interrupt Request Timing....................... 146
Asynchronous Serial Interface Reception Completion Interrupt Request Timing............................ 147
Receive Error Timing....................................................................................................................... 148