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Preliminary Product Information
59
μ
PD789186, 789187, 789196, 789197
Figure 6-28. A/D Converter Block Diagram
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
Sample-and-hold circuit
Voltage comparator
Control
circuit
Successive
approximation
register (SAR)
3
A/D conversion result
register 0 (ADCR0)
T
S
AV
SS
INTAD
A/D conveter mode register 0
(ADM0)
A/D input selection register 0
(ADS0)
Internal bus
AV
SS
ADCS0
0
FR02 FR01 FR00
0
0
0
ADS02ADS01ADS00
AV
REF
AV
DD
(1) Successive approximation register (SAR)
The SAR receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison
voltage), received from the serial resistor string, starting from the most significant bit (MSB).
Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D
conversion, the SAR sends its contents to the A/D conversion result register.
(2) A/D conversion result register 0 (ADCR0)
The ADCR holds the result of A/D conversion. Each time A/D conversion ends, the conversion result received
from the successive approximation register is loaded into the ADCR0.
For the
μ
PD789186 and
μ
PD789187 (featuring 8-bit A/D converters), the value of ADCR0 is read using an 8-
bit memory manipulation instruction.
For the
μ
PD789196 and
μ
PD789197 (featuring 10-bit A/D converters), the value of ADCR0 is read using a 16-
bit memory manipulation instruction.
The value of this register becomes undefined upon the input of a RESET signal.
(3) Sample-and-hold circuit
The sample-and-hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends
them to the voltage comparator. The sampled analog input voltage is held during A/D conversion.
(4) Voltage comparator
The voltage comparator compares an analog input with the voltage output by the serial resistor string.