![](http://datasheet.mmic.net.cn/380000/-PD789187_datasheet_16744969/-PD789187_21.png)
Preliminary Product Information
21
μ
PD789186, 789187, 789196, 789197
Table 4-1. Special Function Registers (2/3)
Address Special function register (SFR) name
Symbol
R/W
Number of bits manipulated simultaneously
When reset
1 bit
8 bits
16 bits
FF48H
16-bit timer mode control register 90
TMC90
R/W
{
{
00H
FF49H
Buzzer output control register 90
BZC90
{
{
FF4AH
Clock timer mode control register
WTM
{
{
FF50H
8-bit compare register 80
CR80
W
{
Undefined
FF51H
8-bit timer register 80
TM80
R
{
00H
FF53H
8-bit timer mode control register 80
TMC80
R/W
{
{
FF54H
8-bit compare register 81
CR81
W
{
Undefined
FF55H
8-bit timer register 81
TM81
R
{
00H
FF57H
8-bit timer mode control register 81
TMC81
R/W
{
{
FF58H
8-bit compare register 82
CR82
W
{
Undefined
FF59H
8-bit timer register 82
TM82
R
{
00H
FF5BH
8-bit timer mode control register 82
TMC82
R/W
{
{
FF70H
Asynchronous serial interface mode
register 20
ASIM20
{
{
FF71H
Asynchronous serial interface
status register 20
ASIS20
R
{
FF72H
Serial operation mode register 20
CSIM20
R/W
{
{
FF73H
Baud rate generator control register
20
BRGC20
{
{
FF74H
Transmission shift register 20
TXS20
SIO20
W
{
FFH
Reception buffer register 20
RXB20
R
{
Undefined
FF78H
SMB control register 0
SMBC0
R/W
{
{
00H
FF79H
SMB status register 0
SMBS0
R
{
{
FF7AH
SMB clock selection register 0
SMBCL0
R/W
{
{
FF7BH
SMB slave address register 0
SMBSVA0
{
{
FF7CH
SMB mode register 0
SMBM0
{
{
20H
FF7DH
SMB input level setting register 0
SMBVI0
{
{
00H
FF7EH
SMB shift register 0
SMB0
{
{
FF80H
A/D converter mode register 0
ADM0
{
{
FF84H
A/D input selection register 0
ADS0
{
{
FFCCH
EEPROM write control register 0
EEWC0
{
{
04H
FFD0H
Multiplication data register A0
MRA0
W
{
{
Undefined
FFD1H
Multiplication data register B0
MRB0
{
{
FFD2H
Multiplier control register 0
MULC0
R/W
{
{
00H
FFDFH
Low-voltage indicator register 0
LVI0
{
{
FFE0H
Interrupt request flag register 0
IF0
{
{
FFE1H
Interrupt request flag register 1
IF1
{
{
FFE2H
Interrupt request flag register 2
IF2
{
{