![](http://datasheet.mmic.net.cn/380000/-PD789167Y_datasheet_16744965/-PD789167Y_109.png)
Preliminary Product Information
108
μ
PD789166Y, 789167Y, 789176Y, 789177Y
Table 8-1. State of the Hardware after a Reset (1/2)
Hardware
State after reset
Program counter (PC)
Note 1
Loaded with the contents of
the reset vector table
(0000H, 0001H)
Stack pointer (SP)
Undefined
Program status word (PSW)
02H
RAM
Data memory
Undefined
Note 2
General-purpose register
Undefined
Note 2
Ports (P0 to P3, P5, P6) (output latch)
00H
Port mode registers (PM0 to PM3, PM5)
FFH
Pull-up resistor option registers (PU0, PUB2, PUB3)
00H
Processor clock control register (PCC)
02H
Suboscillation mode register (SCKM)
00H
Subclock control register (CSS)
00H
Oscillation settling time selection register (OSTS)
04H
16-bit timer/counter 90
Timer register (TM90)
0000H
Compare register (CR90)
FFFFH
Capture register (TCP90)
Undefined
Mode control register (TMC90)
00H
Buzzer output control register (BZC90)
00H
Timer registers (TM80 to TM82)
00H
Compare registers (CR80 to CR82)
Undefined
Mode control registers (TMC80 to TMC82)
00H
Clock timer
Mode control register (WTM)
00H
Watchdog timer
Timer clock selection register (TCL2)
00H
Mode register (WDTM)
00H
A/D converter
Mode register (ADM0)
00H
A/D input selection register (ADS0)
00H
A/D conversion result register (ADCR0)
Undefined
Serial interface 20
Mode register (CSIM20)
00H
Asynchronous serial interface mode register (ASIM20)
00H
Asynchronous serial interface status register (ASIS20)
00H
Baud rate generator control register (BRGC20)
00H
Transmission shift register (TXS20)
FFH
Reception buffer register (RXB20)
Undefined
Notes 1.
While a reset signal is being input, and during the oscillation settling period, the contents of the PC will
be undefined, while the remainder of the hardware will be the same as after the reset.
2.
In standby mode, the RAM enters the hold state after a reset.
8-bit timer/event counters 80
to 82