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CHAPTER 5 ADDRESSING
5.2.1 Implied addressing
[Function]
This type of addressing automatically addresses registers in the register bank specified by the register bank
selection flags (RBS2, RBS1, and RBS0).
Instructions that use implied addressing in the 78K/IV Series instruction word are shown below.
The A, AX, C, and B registers used by these instructions are affected by the RSS bit in the PSW. When RSS =
0, R1, RP0, R2, and R2, respectively are accessed for the A, AX, C, and B registers, and when RSS = 1, R5, RP2,
R6, and R7 are accessed. RSS should only be set to 1 when a 78K/III Series program is used (see
3.1.3 Use
of RSS bit
).
Instruction
Registers Specified by Implied Addressing
MULU
A register as multiplicand, AX register as that holds product
MULUW, MULW
AX register as multiplicand and register that holds high-order 16 bits of product
DIVUW
AX register as register that holds dividend and quotient
DIVUX
AXDE register as register that holds dividend and quotient
MACW, MACSW
AXDE register as register that holds result of sum of products operation, B and C registers as
pointer registers that specify data
ADJBA, ADJBS
A register as register that holds numeric value subject to decimal adjustment
CVTBW
A register as register that holds data before sign extension is performed, and AX register as
register that holds result of sign extension
CHKLA
A register as register that holds result of comparison between pin level and port output latch
ROR4, ROL4
A register as register that holds digit data subject to digit rotation (only low-order 4 bits are
used)
SACW, string instruction
C register as data counter string instruction
[Operand Format]
As this is used automatically according to the instruction, there is no specific operand format.
[Description Example]
MULU r; In an 8-bit x 8-bit multiplication instruction, the product of the A register and r register are stored in the
AX register. Here, the A and AX registers are specified by implied addressing.