![](http://datasheet.mmic.net.cn/380000/-PD784928Y_datasheet_16744934/-PD784928Y_207.png)
207
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B2
B3
B4
B5
B6
B7
MOVW
AX, [WHL + A]
0 0 0 1
0 1 1 1
0 0 0 1
0 0 0 1
AX, [TDE + B]
0 0 0 1
0 1 1 1
0 0 1 0
0 0 0 1
AX, [WHL + B]
0 0 0 1
0 1 1 1
0 0 1 1
0 0 0 1
AX, [VVP + DE]
0 0 0 1
0 1 1 1
0 1 0 0
0 0 0 1
AX, [VVP + HL]
0 0 0 1
0 1 1 1
0 1 0 1
0 0 0 1
AX, [TDE + C]
0 0 0 1
0 1 1 1
0 1 1 0
0 0 0 1
AX, [WHL + C]
0 0 0 1
0 1 1 1
0 1 1 1
0 0 0 1
[saddrp2], AX
0 0 0 0
0 1 1 1
1 0 1 0
0 0 0 1
←
Saddr2-offset
→
[saddrp1], AX
0 0 1 1
--------------------------------------------------------------------------------
1 1 0 0
0 0 0 0
0 1 1 1
1 0 1 0
0 0 0 1
←
Saddr1-offset
→
[%saddrg2], AX
0 0 0 0
0 1 1 1
1 0 1 1
0 0 0 1
←
Saddr2-offset
→
[%saddrg1], AX
0 0 1 1
--------------------------------------------------------------------------------
1 1 0 0
0 0 0 0
0 1 1 1
1 0 1 1
0 0 0 1
←
Saddr1-offset
→
[TDE +], AX
0 0 0 1
0 1 1 0
1 0 0 0
0 0 0 1
[WHL +], AX
0 0 0 1
0 1 1 0
1 0 0 1
0 0 0 1
[TDE –], AX
0 0 0 1
0 1 1 0
1 0 1 0
0 0 0 1
[WHL–], AX
0 0 0 1
0 1 1 0
1 0 1 1
0 0 0 1
[TDE], AX
0 0 0 1
0 1 1 0
1 1 0 0
0 0 0 1
[WHL], AX
0 0 0 1
0 1 1 0
1 1 0 1
0 0 0 1
[VVP], AX
0 0 0 1
0 1 1 0
1 1 1 0
0 0 0 1
[UUP], AX
0 0 0 1
0 1 1 0
1 1 1 1
0 0 0 1
[TDE + byte], AX
0 0 0 0
0 1 1 0
1 0 0 0
0 0 0 1
←
Low Offset
→
[SP + byte], AX
0 0 0 0
0 1 1 0
1 0 0 1
0 0 0 1
←
Low Offset
→
[WHL + byte], AX
0 0 0 0
0 1 1 0
1 0 1 0
0 0 0 1
←
Low Offset
→
[UUP + byte], AX
0 0 0 0
0 1 1 0
1 0 1 1
0 0 0 1
←
Low Offset
→
[VVP + byte], AX
0 0 0 0
0 1 1 0
1 1 0 0
0 0 0 1
←
Low Offset
→
imm24 [DE], AX
0 0 0 0
--------------------------------------------------------------------------------
1 0 1 0
1 0 0 0
0 0 0 1
←
Low Offset
→
←
High Offset
→
←
High-w Offset
→
imm24 [A], AX
0 0 0 0
--------------------------------------------------------------------------------
1 0 1 0
1 0 0 1
0 0 0 1
←
Low Offset
→
←
High Offset
→
←
High-w Offset
→
imm24 [HL], AX
0 0 0 0
--------------------------------------------------------------------------------
1 0 1 0
1 0 1 0
0 0 0 1
←
Low Offset
→
←
High Offset
→
←
High-w Offset
→
imm24 [B], AX
0 0 0 0
--------------------------------------------------------------------------------
1 0 1 0
1 0 1 1
0 0 0 1
←
Low Offset
→
←
High Offset
→
←
High-w Offset
→
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