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CHAPTER 5 ADDRESSING
5.2.2 Register addressing
[Function]
This type of addressing accesses as an operand the general register specified by the register specification code
in the instruction word in the register bank specified by the register bank selection flag (RBS2, RBS1, RBS0).
Register addressing is performed when an instruction with one of the operand formats shown below is executed.
[Operand Format]
Performed when an instruction with one of the operand formats shown below is executed.
Identifier
Description Format
A
A
C
C
X
X
B
B
r
X(R0), A(R1), C(R2), B(R3), R4, R5, R6, R7, R8, R9, R10, R11, E(R12), D(R13), L(R14), H(R15)
r1
X(R0), A(R1), C(R2), B(R3), R4, R5, R6, R7
r2
R8, R9, R10, R11, E(R12), D(R13), L(R14), H(R15)
r3
V, U, T, W
AX
AX
rp
AX(RP0), BC(RP1), RP2, RP3, VP(RP4), UP(RP5), DE(RP6), HL(RP7)
rp1
AX(RP0), BC(RP1), RP2, RP3
rp2
VP(RP4), UP(RP5), DE(RP6), HL(RP7)
WHL
WHL
rg
VVP(RG4), UUP(RG5), TDE(RG6), WHL(RP7)
Remarks 1.
Absolute names are shown in parentheses.
2.
With an instruction (such as ADDW AX, #word) in which A, X, AX, B, or C is specified directly as
the register addressing operand, the register used as A, X, AX, B, or C is determined by the RSS
bit in the PSW when the instruction is executed. The RSS bit in the PSW should be set to “1” only
when a 78K/III Series program is used (see
3.1.3 Use of RSS bit
).
3.
If A, X, B, C, AX, or BC is written as an operand in an instruction in which r, r1, rp, or rp1 is specified
as the register addressing operand, with the NEC RA78K4 assembler the object code generated
depends on the RSS pseudo-instruction written immediately before. “1” should be specified in the
RSS pseudo-instruction operand only when a 78K/III Series program is used (see
3.1.3 Use of RSS
bit
).
[Description Example 1]
General example
MOV A, r
Specific example
MOV A, C ; When the C register is selected as r
[Description Example 2]
General example
INCW rp
Specific example
INCW DE ; When the DE register pair is selected as rp