26
19-13.
19-14.
19-15.
19-16.
3-wire Serial I/O Mode Timing ............................................................................................
Circuit of Switching in Transfer Bit Order ...........................................................................
Reception Completion Interrupt Request Generation Timing (When ISRM = 1) ................
Receive Buffer Register Read Disable Period....................................................................
461
462
463
464
20-1.
20-2.
20-3.
20-4.
20-5.
Real-time Output Port Block Diagram ................................................................................
Real-time Output Buffer Register Configuration .................................................................
Port Mode Register 12 Format ...........................................................................................
Real-time Output Port Mode Register Format ....................................................................
Real-time Output Port Control Register Format .................................................................
468
469
470
470
471
21-1.
21-2.
21-3.
21-4.
21-5.
21-6.
21-7.
21-8.
21-9.
21-10.
21-11.
21-12.
21-13.
21-14.
21-15.
21-16.
21-17.
21-18.
21-19.
21-20.
21-21.
Basic Configuration of Interrupt Function ...........................................................................
Interrupt Request Flag Register Format .............................................................................
Interrupt Mask Flag Register Format..................................................................................
Priority Specify Flag Register Format.................................................................................
External Interrupt Mode Register 0 Format ........................................................................
External Interrupt Mode Register 1 Format ........................................................................
Sampling Clock Select Register Format.............................................................................
Noise Eliminator Input/Output Timing (During Rising Edge Detection) ..............................
Program Status Word Format.............................................................................................
Non-Maskable Interrupt Request Occurrence and Acknowledge Flowchart ......................
Non-Maskable Interrupt Request Acknowledge Timing......................................................
Non-Maskable Interrupt Request Acknowledge Operation ................................................
Interrupt Request Acknowledge Processing Algorithm.......................................................
Interrupt Request Acknowledge Timing (Minimum Time) ...................................................
Interrupt Request Acknowledge Timing (Maximum Time) ..................................................
Multiple Interrupt Example..................................................................................................
Interrupt Request Hold .......................................................................................................
Basic Configuration of Test Function ..................................................................................
Format of Interrupt Request Flag Register 1L ....................................................................
Format of Interrupt Mask Flag Register 1L.........................................................................
Key Return Mode Register Format.....................................................................................
476
479
480
481
482
483
484
485
486
488
488
489
491
492
492
494
496
497
498
498
499
22-1.
22-2.
22-3.
22-4.
22-5.
22-6.
22-7.
22-8.
Memory Map when Using External Device Expansion Function ........................................
Memory Expansion Mode Register Format ........................................................................
Memory Size Switching Register Format ...........................................................................
Instruction Fetch from External Memory ............................................................................
External Memory Read Timing ...........................................................................................
External Memory Write Timing ...........................................................................................
External Memory Read Modify Write Timing ......................................................................
Connection Example of
μ
PD780054 and Memory .............................................................
502
505
506
508
509
510
511
512
23-1.
23-2.
Oscillation Stabilization Time Selection Register Format ...................................................
HALT Mode Release by Interrupt Request Generation ......................................................
514
516
LIST OF FIGURES (7/8)
Figure No.
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