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CHAPTER 4 PIN FUNCTION (
μ
PD780024Y, 780034Y SUBSERIES)
(1) Port Pins (2/2)
(2) Non-port Pins (1/2)
Pin Name
Input/Output
Function
After Reset
Alternate
Function
P70
Input/Output
Input
TI00/TO0
P71
TI01
P72
TI50/TO50
P73
TI51/TO51
P74
PCL
P75
BUZ
Port 7
6-bit input/output port
Input/output mode can be specified bit-wise.
If used as an input port, an on-chip pull-up resistor can be
used by software.
Pin Name
Input/Output
Function
After Reset
Alternate
Function
INTP0
Input
Input
P00
INTP1
P01
INTP2
P02
INTP3
P03/ADTRG
SI30
Input
Serial interface serial data input
Input
P20
SO30
Output
Serial interface serial data output
Input
P21
SDA0
Input/Output
Serial interface serial data input/output
Input
P32
SCK30
Input/Output
Serial interface serial clock input/output
Input
P22
SCL0
P33
RxD0
Input
Asynchronous serial interface serial data input
Input
P23
TxD0
Output
Asynchronous serial interface serial data output
Input
P24
ASCK0
Input
Asynchronous serial interface serial clock input
Input
P25
TI00
Input
External count clock input to 16-bit timer (TM0)
Capture trigger input to TM0 capture register (CR01)
Input
P70/TO0
TI01
Capture trigger input to TM0 capture register (CR00)
P71
TI50
External count clock input to 8-bit timer (TM50)
P72/TO50
TI51
External count clock input to 8-bit timer (TM51)
P73/TO51
TO0
Output
16-bit timer TM0 output
Input
P70/TI00
TO50
8-bit timer (TM50) output (also used for 8-bit PWM output)
Input
P72/TI50
TO51
8-bit timer (TM51) output (also used for 8-bit PWM output)
P73/TI51
PCL
Output
Clock output (for main system clock and subsystem clock
trimming)
Input
P74
BUZ
Output
Buzzer output
Input
P75
AD0 to AD7
Input/Output
Lower-order address/data bus when expanding external memory
Input
P40 to P47
A8 to A15
Output
High-order address bus when expanding external memory
Input
P50 to P57
RD
Output
Strobe signal output for read operation from external memory
Input
P64
WR
Strobe signal output for write operation from external memory
P65
WAIT
Input
Wait insertion when accessing external memory
Input
P66
ASTB
Output
Strobe output externally latching address information
output to ports 4, 5 to access external memory
Input
P67
External interrupt request input with specifiable valid edges
(rising edge, falling edge, both rising and falling edges)