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CHAPTER 18 SERIAL INTERFACE (IIC0) (
μ
PD780024Y, 780034Y SUBSERIES ONLY)
18.2 Serial Interface Configuration
The serial interface (IIC0) includes the following hardware.
Table 18-1. Serial Interface (IIC0) Configuration
Item
Configuration
Registers
IIC shift register (IIC0)
Slave address register (SVA0)
Control registers
IIC control register (IICC0)
IIC status register (IICS0)
IIC clock select register (IICCL0)
(1) IIC shift register (IIC0)
IIC0 is used to convert 8-bit serial data to 8-bit parallel data and to convert 8-bit parallel data to 8-bit serial data.
IIC0 can be used for both transmission and reception.
Write and read operations to IIC0 are used to control the actual transmit and receive operations.
IIC0 is set by an 8-bit memory manipulation instruction.
RESET input sets the IIC0 00H.
(2) Slave address register (SVA0)
This register sets local addresses when in slave mode.
SVA0 is set by an 8-bit memory manipulation instruction.
RESET input sets SVA0 to 00H.
(3) SO0 latch
The SO0 latch is used to retain the SDA0 pin’s output level.
(4) Wake-up control circuit
This circuit generates an interrupt request when the address received by this register matches the address value
set to the slave address register (SVA0) or when an extension code is received.
(5) Clock selector
This selects the sampling clock to be used.
(6) Serial clock counter
This counter counts the serial clocks that are output or input during transmit/receive operations and is used to
verify that 8-bit data was sent or received.
(7) Interrupt request signal generator
This circuit controls the generation of interrupt request signals (INTIIC0).
An I
2
C interrupt request is generated following either of two triggers.
Eighth or ninth clock of the serial clock (set by WTIM0 bit)
Note
Interrupt request generated when a stop condition is detected (set by SPIE0 bit)
Note
Note
WTIM0 bit : bit 3 of the IIC control register (IICC0)
SPIE0 bit : bit 4 of the IIC control register (IICC0)