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參數(shù)資料
| 型號： | μPD703008 |
| 廠商： | NEC Corp. |
| 英文描述： | 16/32 Bit RISC Microcontrollers(16/32位RISC微控制器) |
| 中文描述： | 16/32位RISC微控制器（16/32位的RISC微控制器） |
| 文件頁數(shù)： | 124/141頁 |
| 文件大?。?/td> | 374K |
| 代理商： | ΜPD703008 |
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CHAPTER 8 PIPELINE
112
As described above, when an instruction placed immediately after a multiply instruction uses its execution result,
a data wait time occurs due to the interlock function, and the execution speed is lowered. This drop in execution speed
can be avoided by placing instructions that use the execution result of a multiply instruction at least 2 instructions
after the multiply instruction.
8.3.4 Referencing execution result of LDSR instruction for EIPC and FEPC
When using the LDSR instruction to set the data of the EIPC and FEPC system registers, and immediately after
referencing the same system registers with the STSR instruction, the use of the system registers for the STSR
instruction is delayed until the setting of the system registers with the LDSR instruction is completed (occurrence of
hazard).
The V850 family’s interlock function delays the ID stage of the STSR instruction immediately after.
As a result of the above, when using the execution result of the LDSR instruction for EIPC and FEPC for an STSR
instruction following immediately after, the number of execution clocks of the LDSR instruction becomes 3.
IL :
– :
Idle inserted for data wait by interlock function
Idle inserted for wait
Note
System register 0 used for the LDSR and STSR instructions designates EIPC.
As described above, when an STSR instruction is placed immediately after an LDSR instruction that uses the
operand EIPC or FEPC, and that STSR instruction uses the LDSR instruction execution result, the interlock function
causes a data wait time to occur, and the execution speed is lowered. This drop in execution speed can be avoided
by placing STSR instructions that reference the execution result of the preceding LDSR instruction at least 3
instructions after the LDSR instruction.
8.3.5 Cautions when creating programs
When creating programs, pipeline disorder can be avoided and instruction execution speed can be raised by
observing the following cautions.
Place instructions that use the execution result of load instructions (LD, SLD) at least 2 instructions after the
load instruction.
Place instructions that use the execution result of multiply instructions (MULH, MULHI) at least 2 instructions
after the multiply instruction.
If using the STSR instruction to read the setting results written to the EIPC or FEPC registers with the LDSR
instruction, place the STSR instruction at least 3 instructions after the LDSR instruction.
For the first branch destination instruction, use a 2-byte instruction, or a 4-byte instruction placed at the word
boundary.
IF
ID
IF
EX
IL
IF
MEM
IL
–
EX
ID
IF
LDSR instruction
(LDSR R6, 0)
Note
STSR instruction
(STSR 0, R7)
Note
Next instruction
Next to next instruction
MEM
EX
ID
–
MEM
EX
MEM
WB
WB
WB
WB
ID
1
2
3
4
5
6
7
8
9
10
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