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參數(shù)資料
| 型號： | μPD703008 |
| 廠商： | NEC Corp. |
| 英文描述： | 16/32 Bit RISC Microcontrollers(16/32位RISC微控制器) |
| 中文描述： | 16/32位RISC微控制器（16/32位的RISC微控制器） |
| 文件頁數(shù)： | 122/141頁 |
| 文件大?。?/td> | 374K |
| 代理商： | ΜPD703008 |
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CHAPTER 8 PIPELINE
110
8.3 Pipeline Disorder
The pipeline consists of 5 stages from IF (Instruction Fetch) to WB (Write Back). Each stage basically requires
1 clock for processing, but the pipeline may become disordered, causing the number of execution clocks to increase.
This section describes the main causes of pipeline disorder.
8.3.1 Alignment hazard
If the branch destination instruction address is not word aligned (A1=1, A0=0) and is 4 bytes in length, it is necessary
to repeat IF twice in order to align instructions in word units. This is called align hazard.
For example, let us suppose that instructions a to e are placed from address X0H, and that instruction b consists
of 4 bytes, and the other instructions each consist of 2 bytes. In this case, instruction b is placed at X2H (A1=1, A0=0),
and is not word aligned (A1=0, A0=0). Therefore, when this instruction b becomes the branch destination instruction,
an align hazard occurs. When an align hazard occurs, the number of execution clocks of the branch instruction
becomes 4.
Figure 8-3. Align Hazard Example
(a) Memory map
(b) Pipeline
IF x :
–
IF1 :
Instruction fetch that is not executed
Idle inserted for wait
First instruction fetch that occurs during align hazard. It is a 2-byte
fetch that fetches the 2 bytes on the lower address of instruction
b.
Second instruction fetch that occurs during align hazard. It is
normally a 4-byte fetch that fetches the 2 bytes on the upper
address of instruction b in addition to instruction c (2-byte length).
:
IF2 :
Align hazard can be prevented through the following handling in order to obtain faster instruction execution.
Use 2-byte branch destination instruction.
Use 4-byte instructions placed at word boundaries (A1=0, A0=0) for branch destination instructions.
Instruc-
tion d
Instruc-
tion e
Instruc-
tion b
Instruc-
tion c
Instruc-
tion a
Instruc-
tion b
X8H
X4H
X0H
32 bits
Address of branch destination
instruction (instruction b)
IF
ID
IF
×
EX
–
IF
×
MEM
WB
Branch instruction
Next instruction
Next to next instruction
Branch destination instruction (instruction b)
Branch destination’s next instruction (instruction c)
1
2
3
4
5
6
7
8
IF1
IF2
ID
IF
EX
ID
MEM
EX
WB
MEM
WB
9
10
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