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參數(shù)資料
| 型號： | μPD431536L |
| 廠商： | NEC Corp. |
| 英文描述： | 1M-Bit CMOS Synchronous Fast Static RAM(1M CMOS 同步快速靜態(tài)RAM) |
| 中文描述： | 100萬位CMOS同步快速靜態(tài)RAM（100萬的CMOS同步快速靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 166K |
| 代理商： | ΜPD431536L |
MOS INTEGRATED CIRCUIT
μ
PD431536L
The information in this document is subject to change without notice.
1997
1M-BIT CMOS SYNCHRONOUS FAST SRAM
32K-WORD BY 36-BIT
FLOW THROUGH OPERATION
Document No. M12389EJ5V0DS00 (5th edition)
Date Published July 1998 NS CP(K)
Printed in Japan
DATA SHEET
The mark
shows major revised points.
Description
The
μ
PD431536L is a 32,768-word by 36-bit synchronous static RAM fabricated with advanced CMOS technology
using N-channel four-transistor memory cell.
The
μ
PD431536L integrates unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as
SRAM core. All input registers are controlled by a positive edge of the single clock input (CLK).
The
μ
PD431536L is suitable for applications which require synchronous operation, high speed, low voltage, high
density and wide bit configuration, such as cache and buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”).
In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal
operation.
The
μ
PD431536LGF is packaged in 100-pin plastic LQFP with a 1.4 mm package thickness for high density and low
capacitive loading.
Features
3.3 V (Chip) / 3.3 V or 2.5 V (I/O) Supply
Synchronous Operation
Internally self-timed Write control
Burst Read / Write: Interleaved Burst and Linear Burst Sequence
Fully Registered Inputs for Flow Through Operation
All Registers triggered off Positive Clock Edge
3.3V or 2.5V LVTTL Compatible : All Inputs and Outputs
Fast Clock Access Time: 8.5 ns (100 MHz), 9 ns (100 MHz), 10 ns (83 MHz), 12 ns (66 MHz)
Asynchronous Output Enable: /G
Burst Sequence Selectable: MODE
Sleep Mode: ZZ (ZZ = Open or Low : Normal Operation)
Separate Byte Write Enable: /BW1 - /BW4, /BWE
Global Write Enable: /GW
Three Chip Enables for Easy Depth Expansion
Common I/O Using Three State Outputs
Ordering Information
Part number
μ
PD431536LGF-A8
μ
PD431536LGF-A9
μ
PD431536LGF-A10
μ
PD431536LGF-A12
Access Time Clock frequency
8.5 ns
9 ns
10 ns
12 ns
Package
100 MHz
100 MHz
83 MHz
66 MHz
100-pin plastic LQFP (14 x 20 mm)
100-pin plastic LQFP (14 x 20 mm)
100-pin plastic LQFP (14 x 20 mm)
100-pin plastic LQFP (14 x 20 mm)
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