參數(shù)資料
型號(hào)： μPD42S65405
廠商： NEC Corp.
英文描述： 16,777,216 Words by 4 Bits CMOS Dynamic RAMs(64M 動(dòng)態(tài)RAM)
中文描述： 16,777,216詞由4位的CMOS動(dòng)態(tài)存儲(chǔ)器（RAM的6400動(dòng)態(tài)）
文件頁(yè)數(shù)： 7/36頁(yè)
文件大?。?/td> 256K
代理商： ΜPD42S65405
μ
PD4264405, 42S65405, 4265405
7
Cautions when using the hyper page mode (EDO)
1.
CAS access should be used to operate t
HPC
at the MIN. value.
2.
To make I/Os to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on the state of each signal.
(1) Both RAS and CAS are inactive (at the end of read cycle)
WE: inactive, OE: active
t
OFC
is effective when RAS is inactivated before CAS is inactivated.
t
OFR
is effective when CAS is inactivated before RAS is inactivated.
The slower of t
OFC
and t
OFR
becomes effective.
(2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ····· t
OEZ
is effective.
Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either t
RRH
or t
RCH
must be met ····· t
WEZ
and t
WPZ
are effective.
The faster of t
OEZ
and t
WEZ
becomes effective.
The faster of (1) and (2) becomes effective.
3.
In read cycle, the effective specification depends on the state of CAS signal when controlling data output
with the OE signal.
(1) CAS: inactive, OE: active ····· t
CHO
is effective.
(2) CAS, OE: active ····· t
OCH
is effective.
相關(guān)PDF資料
PDF描述
μPD4264405 16,777,216 Words by 4 Bits CMOS Dynamic RAMs(64M 動(dòng)態(tài)RAM)
μPD4265405 16,777,216 Words by 4 Bits CMOS Dynamic RAMs(64M 動(dòng)態(tài)RAM)
μPD42S65805 8,388,608 Words by 8 Bits CMOS dynamic RAMs(64M 動(dòng)態(tài)RAM)
μPD4264805 8,388,608 Words by 8 Bits CMOS dynamic RAMs(64M 動(dòng)態(tài)RAM)
μPD4265805 8,388,608 Words by 8 Bits CMOS dynamic RAMs(64M 動(dòng)態(tài)RAM)
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