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| 型號： | ZPSD403A2 |
| 英文描述： | Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個可編程I/O,通用PLD有59個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備（可編程邏輯，零功耗，16K的位的SRAM，40余個可編程輸入/輸出，通用PLD的有59個輸入） |
| 文件頁數(shù)： | 4/108頁 |
| 文件大?。?/td> | 626K |
| 代理商： | ZPSD403A2 |
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ZPSD4XX Famly
5-4
The ZPSD4XX series of Field Programmable Microcontroller Peripherals represent a
major advance in the evolution of Programmable Peripherals. They combine an innovative
architecture with state of the art technology to provide user programmability (logic,
functions, memory), flexibility, high integration, optimum performance, and low power . For
example, the PSD413A2 can implement a full peripheral subsystem and has the following
features:
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Two ZPLDs with a total of 59 inputs, 126 product terms outputs, 24 macrocells
and 24 I/O pins.
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40 individually programmable I/O pins that are divided into 5 Ports.
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4-Bit Page Register for external memory addressing
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1 Mbit EPROM consisting of four 256 Kbit blocks.
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16 Kbit of standby SRAM that can automatically switch into standby mode.
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Power management unit with automatic standby and sleep modes.
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Security mode.
Figure 2 is a top level block diagram of the ZPSD4XX. Refer to Table 1 and other sections
for details on functionality, DC/AC specifications, packages and ordering information.
At the core of the ZPSD4XX are ZPLDs dedicated to the functions they perform:
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Decoding ZPLD (DPLD)
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General Purpose ZPLD (GPLD)
Both ZPLDs receive the same inputs through the ZPLD bus and are differentiated by their
output destinations. The Decoder PLD (DPLD) has as its main function to perform address
space decoding for the internal I/O Ports, four blocks of EPROM, standby SRAM and
peripheral mode of Port A. The address decoding can be based on any address input,
control signal (RD, PSEN, etc.) and page logic. Address inputs originate from either the
microcontroller interface (ADIO Port) or other I/O Ports for additional decoding. The DPLD
also supports special requirements of 8031 architecture based designs that need to store
data in the EPROM or execute programs from the SRAM.
The general purpose PLD (GPLD) is a general purpose ZPLD that can be used to
implement state machines and logic . The GPLD has up to 59 inputs, 118 product terms,
24 flexible macrocells and 24 I/O pins that are connected to Ports A, B and E. The GPLD
can also decode the microcontroller address bus and generate chip selects to external
peripherals or memories.
The ZPLDs are designed to consume minimum power using Zero Power design techniques.
A configuration bit (Turbo bit), that can be set by the MCU, will automatically place the
ZPLDs into standby if no inputs are changing. Any unused product terms will be turned off
during programming and will not consume any power in the system.
The ZPSD4XX has 40 I/O pins that are divided into 5 ports. Each I/O pin can be individually
configured to provide many functions. Ports A, B and E have the capability to be configured
as standard MCU I/O ports, GPLD I/O, or latched address outputs for multiplexed
address/data controllers. Ports C and D are standard I/O ports that can also be configured
as ZPLD inputs or as a data bus for microcontrollers with a non-multiplexed bus.
The ZPSD4XX can easily interface with no “glue-logic” to a variety of 8 and 16-bit
microcontrollers with a multiplexed or non-multiplexed bus. All of the control signals are
connected to the two ZPLDs enabling the user to generate timing and decoding signals for
external peripherals. For controllers that do not have a Reset output, the ZPSD4XX can
generate a RESET output based on its RESET input. This input includes hysteresis.
General
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZPSD412A1 | Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個可編程I/O,通用PLD有37個輸入) |
| ZPSD412A2 | Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個可編程I/O,通用PLD有59個輸入) |
| ZPSD402A1 | Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個可編程I/O,通用PLD有37個輸入) |
| ZPSD402A2 | Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個可編程I/O,通用PLD有59個輸入) |
| ZPSD411A1 | Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個可編程I/O,通用PLD有37個輸入) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZPSD403A2-12J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| ZPSD403A2-12JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| ZPSD403A2-12LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| ZPSD403A2-12U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| ZPSD403A2-12UI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
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