ZPSD3XX Famly
3-6
Product
Description
The ZPSD3XX family integrates high performance user-configurable zero-power blocks of
EPROM, SRAM, and zero-power programmable logic. The major functional blocks include
two programmable logic arrays, PAD A and PAD B, 256K to 2Mbit of EPROM, 16K bits of
SRAM, input latches, and output ports. The ZPSD3XX family is ideal for applications
requiring very low power and very small form factors. These include hard disk control,
wireless or mobile products, modems, cellular telephones, instrumentation, computer
peripherals, military and similar applications.
The ZPSD3XX family offers a unique single-chip solution for microcontrollers that need:
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I/O reconstruction (microcontrollers lose at least two I/O ports when accessing external
resources).
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More EPROM and SRAM than the microcontroller’s internal memory.
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Chip-select, control, or latched address lines that are otherwise implemented discretely.
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An interface to shared external resources.
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Expanded microcontroller address space.
WSI’s ZPSD3XX Family Architecture (Figure 2) can efficiently interface with, and enhance,
any low-voltage 8- or 16-bit microcontroller system. This is the first solution that provides
microcontrollers with port expansion, latched addresses, page logic, two programmable
logic arrays (PAD A and PAD B), an interface to shared resources, 256K, 512K, 1M or
2M bit EPROM, and 16K bit SRAM on a single chip. The ZPSD3XX family does not require
any glue logic for interfacing to any 8- or 16-bit microcontroller.
The 8051 microcontroller family can take full advantage of the ZPSD3XX’s separate
program and data address spaces. Users of the 68HCXX microcontroller family can change
the functionality of the control signals and directly connect the R/W and E, or the R/W and
DS signals. (Users of 16-bit microcontrollers, including the 80186, 8096, 80196 and
16XXX, can use the ZPSD301/302/303/304R in a 16-bit configuration). Address and data
buses can be configured as separate or multiplexed, whichever is required by the host
processor.
The flexibility of the ZPSD3XX I/O ports permits interfacing to shared resources. The
arbitration can be controlled internally by PAD A outputs. The user can assign the
following functions to these ports: standard I/O pins, chip-select outputs from PAD A and
PAD B, or latched address or multiplexed low-order address/data byte. This enables users
to design add-on systems such as disk drives, modems, etc., that easily interface to the
host bus (e.g., IBM PC, SCSI).
The page register extends the accessible address space of certain microcontrollers from
64 K to 1 M. There are 16 pages that can serve as base address inputs to the PAD, thereby
enlarging the address space of 16 address line microcontrollers by a factor of 16.