參數(shù)資料
型號： ZPSD312
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，16K位SRAM,4位頁寄存器,19個可編程I/O,通用PLD有16個輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設(shè)備（可編程邏輯，零功耗，16K的位的SRAM，4位頁寄存器，19個可編程的I / O，通用PLD的有16個輸入）
文件頁數(shù)： 16/90頁
文件大?。?/td> 491K
代理商： ZPSD312
ZPSD3XX Famly
3-16
Use This Bit
CDATA
CADDRDAT
CEDS
CA19/CSI
CALE
To
Set the data bus width to 8 or 16 bits (ZPSD30X only).
Set the address/data buses to multiplexed or non-multiplexed mode.
Determine the polarity and functionality of read and write. (Note 10)
Set A19/CSI to CSI (power-down) or A19 input.
Set the ALE polarity.
Set Port A either to track the low-order byte of the address/data
multiplexed bus or to select the I/O or address option.
Set the security on or off (a secured part can not be duplicated).
Set the RESET polarity. (Note 10a)
Set PSEN and RD for combined or separate address spaces
(see Figures 10 and 11).
Configure each pin of Port A in multiplexed mode to be an I/O or
address out.
Configure each pin of Port A as an open drain or active CMOS
pull-up output.
Configure each pin of Port B as an I/O or a chip-select output.
CPAF2
CSECURITY
CRESET
COMB/SEP
CPAF1
(8 Bits)
CPACOD
(8 Bits)
CPBF
(8 Bits)
CPBCOD
(8 Bits)
CPCF
(3 Bits)
Configure each pin of Port B as an open drain or active CMOS
pull-up output.
Configure each pin of Port C as an address input or a chip-select output.
CADDHLT
Configure pins A16 – A19 to go through a latch or to have their
latch transparent.
CADLOG
(4 Bits)
Configure A16 – A19 individually as logic or address inputs. (Note 10)
CATD
Configure pins A16–A19 as PAD logic inputs or high-order address
inputs (Note 9).
Determine in non-multiplexed mode if address inputs are transparent
or latched (Note 10).
CLOT
CRRWR
Set the RD/E and WR/V
PP
or R/W pins to RD and WR pulse, or to E
strobe and R/W status (Note 9).
Configure the polarity and control methods of read and write cycles.
(Note 10)
Controls the lower-power mode.
CRRWR
CMISER
Table 4.
ZPSD3XX
Non-Volatile
Configuration
Bits
The ZPSD3XX has three I/O ports (Ports A, B, and C) that are configurable at the bit level.
This permits great flexibility and a high degree of customization for specific applications.
The following is a description of each port. Figure 5 shows the pin structure of Port A.
Port Functions
Configuration
Bits
The configuration bits shown in Table 4 are non-volatile cells that let the user set the device,
I/O, and control functions to the proper operational mode. Table 5 lists all configuration bits.
The configuration bits are programmed and verified during the programming phase. In
operational mode, they are not accessible. These tables are for information only since to
implement to a specific mode, the PSD Development software will automatically set the
configuration bits by using simple interactive menus.
NOTES:
9. ZPSD3X1 only.
10. Not available on ZPSD3X1 versions.
10a Not available on ZPSD3XXV versions.
相關(guān)PDF資料
PDF描述
ZPSD303 Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，16K位SRAM,19個可編程I/O,通用PLD有16個輸入)
ZPSD313 Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，16K位SRAM,19個可編程I/O,通用PLD有16個輸入)
ZPSD301V Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，16K位SRAM,19個可編程I/O,通用PLD有12個輸入)
ZPSD304R Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，無SRAM,19個可編程I/O,通用PLD有16個輸入)
ZPSD304RV Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，無SRAM,19個可編程I/O,通用PLD有16個輸入)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZPSD312-15LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
ZPSD312-15LM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
ZPSD312-15U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
ZPSD312-15UI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
ZPSD312-70J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
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