參數(shù)資料
型號(hào)： ZPSD304R
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，無SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備（可編程邏輯，零功耗，無的SRAM，19余個(gè)可編程輸入/輸出，通用PLD的有16個(gè)輸入）
文件頁(yè)數(shù)： 8/90頁(yè)
文件大?。?/td> 491K
代理商： ZPSD304R
ZPSD3XX Famly
3-8
Name
Type
BHE/PSEN
(ZPSD30X
Devices)
I
or
PSEN
(ZPSD31X
Devices
Only)
I
WR/V
PP
or
R/W/V
PP
I
RD/E/DS
(Note 2)
I
or
RD/E
(Note 3)
I
Description
When the data bus width is 8 bits (CDATA = 0), this pin is PSEN. In
this mode, PSEN is the active low EPROM read pulse. The ZSRAM
and I/O ports read signal is generated according to the description of
the WR/V
PP
or R/W and RD/E/DS pins. If the host processor is a
member of the 8031 family, PSEN must be connected to the
corresponding host pin. In other 8-bit host processors that do not
have a special EPROM-only read strobe, PSEN should be tied to
V
CC
. In this case, RD or E and R/W provide the read strobe for the
ZSRAM, I/O ports, and EPROM. When the data bus width is
configured as 16 (CDATA = 1), this pin is BHE. When BHE is low,
data bus bits D8–D15 are read from or written into the ZPSD3XX
depending on the operation being read or write, respectively. In
programming mode, this pin is pulsed between V
PP
and 0.
The PSEN is the active low EPROM read pulse. The ZSRAM and I/O
ports read signal is generated according to the description of the
WR/V
PP
or R/W, and RD/E pins. If the host processor is a member
of the 8031 family, PSEN must be connected to the correspondinbg
host pin. In other 8-bit host processors that do not have a special
EPROM-only read strobe, PSEN should be tied to V
CC
. In this case,
RD or E and R/W provide the read strobe for the ZSRAM, I/O ports,
and EPROM.
In the operating mode this pin's function is WR (CRRWR = 0) or
R/W (CRRWR = 1). When configured as R/W, the following tables
summarize the read and write operations (CRRWR = 1):
CEDS = 0
R/W
X
0
1
CEDS = 1 (Note 2)
R/W
DS
X
1
0
0
1
0
E
0
1
1
NOP
write
read
NOP
write
read
When configured as WR, a write operation is executed during an
active low pulse. When configured as R/W, with R/W = 1 and E = 1,
a read operation is executed; if R/W = 0 and E = 1, a write
operation is executed. In programming mode, this pin must be tied
to V
PP
voltage.
The pin function depends on the CRRWR and CEDS configuration
bits. If CRRWR = 0, RD is an active low read pulse. When
CRRWR = 1, this pin and the R/W pin define the following cycle type:
If CEDS = 0, E is an active high strobe. If CEDS = 1, DS is an active
low strobe.
When configured as RD (CRRWR = 0), this pin provides an active
low RD strobe. When configured as E (CRRWR = 1), this pin
becomes an active high pulse, which, together with R/W defines the
cycle type. Then, if R/W = 1 and E = 1, a read operation is executed.
If R/W = 0 and E = 1, a write operation is executed.
Table 1.
ZPSD3XX Pin
Descriptions
Legend:
The I/O column abbreviations are: I = input; I/O = input/output; P = power.
NOTE
:
1. All the configuration bits mentioned in Table 1 appear in parentheses and are explained in
the Configuration Register section.
2. ZPSD3X2/3X3/3X4R only.
3. ZPSD3X1 only.
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