參數(shù)資料
型號(hào): ZPSD303V
英文描述: Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗,16K位SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入)
中文描述: 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備(可編程邏輯,零功耗,16K的位的SRAM,19余個(gè)可編程輸入/輸出,通用PLD的有16個(gè)輸入)
文件頁(yè)數(shù): 10/90頁(yè)
文件大?。?/td> 491K
代理商: ZPSD303V
ZPSD3XX Famly
3-10
Name
Type
PC0
PC1
PC2
I/O
AD0/A0
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
I/O
AD8/A8
AD9/A9
AD10/A10
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15
I/O
GND
P
V
CC
P
Description
This is a 3-bit port for which each bit is configurable as a PAD A
and B input or output. When configured as an input (CPCF = 0),
a bit individually becomes an address (CADLOG = 1 for
ZPSD3X2/3X3/3X4R, CATD = 1 for ZPSD3X1) or a logic input
(CADLOG = 0 for ZPSD3X2/3X3/3X4R, CATD = 0 for ZPSD3X1).
The addresses can be latched with ALE (CADDHLT = 1) or be
transparent inputs to the PADs (CADDHLT = 0). When a pin is
configured as an output (CPCF = 1), it is a function of one product
term of all PAD inputs. See Figure 8.
In multiplexed mode, these pins are the multiplexed low-order
address/data byte. After ALE latches the addresses, these
pins input or output data, depending on the settings of the
RD/E (RD/E/DS on the ZPSD302/312/303/313/304R/314R), WR/V
PP
or R/W, and BHE/PSEN pins. In non-multiplexed mode, these pins
are the low-order address input.
In 16-bit multiplexed mode, these pins are the multiplexed
high-order address/data byte. After ALE latches the addresses, these
pins input or output data, depending on the settings of the RD/E or
RD/E/DS, WR/V
PP
or R/W, and BHE/PSEN pins. In all other modes,
these pins are the high-order address input.
V
SS
(ground) pin.
Supply voltage input.
Table 1.
ZPSD3XX Pin
Descriptions
(Cont.)
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