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| 型號： | ZFBLEWP |
| 英文描述： | ZF-BLE Joint Detection for TD-SCDMA |
| 中文描述： | 迫零線性均衡的聯(lián)合檢測的TD - SCDMA |
| 文件頁數(shù)： | 18/20頁 |
| 文件大小： | 316K |
| 代理商： | ZFBLEWP |
18
5.
Joint Detection Receiver Implementation
Figure 5-1 gives the logical block diagram of the joint detector that has been discussed in this paper. Joint
Detection algorithms are complex and computationally intensive (complexity grows exponentially as the
number of codes increases) and as such are not suitable for use in other CDMA systems because of the high
number of codes used in those systems. In the Joint Detection block diagram, most of the operations are
matrix and vector operations. As the size of the matrices and vectors increases, so does the complexity of
the system and the computational power that is required to separate the users.
Antenna
Data
Data
Extract
e
(a)
Whitening
Matched Filter
A
(a)H
R
n(a)-1
Max Ratio
Antenna
combining
Noise
Variance
Estimation
Matrix
A
(a)
Generaor
Decorrelator
(A
H
R
n-1
A
(a)
)
-1
Max Ratio
Antenna
combining
Calculate
(A
(a)
H
R
n(a)-1
A
(a)
)
-1
Spreading
Code
Generator
Midamble
exraction
e
(a)
Channel
Estimation
User’s data
Figure 5-1 Joint Detection Based Receiver
The analysis of the Joint Detection algorithm presented in this work shows very clearly that a very large of
matrix computations are involved. Because of this, traditional DSPs are not suited to this task. One could
argue that a matrix-coprocessor could be used in the computations, however the variety in the dimensions
of the matrices involved would make such a coprocessor very inefficient and therefore very expensive to
use. An approach with a structure that can reconfigure and adapt would be the ideal solution to the
problem.
The inherent parallelism in the implementation of the various blocks in the Joint Detector makes it an ideal
fit for the Motorola MRC6011 Reconfigurable Compute Fabric. The multicore architecture provides a very
high degree of flexibility and scalability and facilitates the integration of the Joint Detection operation with
the other receiver blocks such as the channel estimation processor. When coupled with Motorola’s
advanced DSPs, the MRC6011 provides the ideal solution for the implementation of a TD-SCDMA
receiver.
For more complete details on the implementation of the receiver with the MRC6011, the reader is referred
to other publications in this series or contact your local Motorola Field Applications Engineer.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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