- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382753 > Z9973BA DIODE TVS 15V 500W UNI-DIR PDF資料下載
參數(shù)資料
| 型號： | Z9973BA |
| 英文描述： | DIODE TVS 15V 500W UNI-DIR |
| 中文描述： | 第十二章分布式輸出時鐘驅(qū)動器| TQFP封裝| 52PIN |塑料 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 63K |
| 代理商： | Z9973BA |
3.3V, 125MHz, Multi-Output Zero Delay Buffer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07089 Rev. **
9/15/2000
Page 2 of 11
Z9973
Pin Description
PIN
11
12
9
10
44, 46, 48, 50
32, 34, 36, 38
16, 18, 21, 23
NAME
PECL_CLK
PECL_CLK#
TCLK0
TCLK1
QA(3:0)
QB(3:0)
QC(3:0)
PWR
I/O
I
I
I
I
O
O
O
TYPE
PU
PD
PU
PU
Description
PECL Clock Input.
PECL Clock Input.
External Reference/Test Clock Input.
External Reference/Test Clock Input.
Clock Outputs. See Table 2 for frequency selections.
Clock Outputs. See Table 2 for frequency selections.
Clock Outputs. See Table 2 for frequency selections.
Feedback Clock Output. Connect to FB_IN for normal operation. The
divider ratio for this output is set by FB_SEL(0:2). See Frequency
Table. A bypass delay capacitor at this output will control Input
Reference/ Output Banks phase relationships.
Synchronous Pulse Output. This output is used for system
synchronization. The rising edge of the output pulse is in sync with
both the rising edges of QA (0:3) and QC(0:3) output clocks
regardless of the divider ratios selected.
Frequency Select Inputs. These inputs select the divider ratio at
QA(0:3) outputs. See Table 2
Frequency Select Inputs. These inputs select the divider ratio at
QB(0:3) outputs. See Table 2
Frequency Select Inputs. These inputs select the divider ratio at
QC(0:3) outputs. See Table 2
Feedback Select Inputs. These inputs select the divide ratio at
FB_OUT output. See Table 1
VCO Divider Select Input. When set low, the VCO output is divided
by 2. When set high, the divider is bypassed. See Table 1
Feedback Clock Input. Connect to FB_OUT for accessing the PLL.
PLL Enable Input. When asserted high, PLL is enabled. And when
low, PLL is bypassed.
Reference Select Input. When high, the PECL clock is selected. And
when low, TCLK (0,1) is the reference clock.
TCLK Select Input. When low, TCLK0 is selected and when high
TCLK1 is selected.
Master Reset/Output Enable Input. When asserted low, resets all of
the internal flip-flops and also disables all of the outputs. When pulled
high, releases the internal flip-flops from reset and enables all of the
outputs.
Inverted Clock Input. When set high, QC(2,3) outputs are inverted.
When set low, the inverter is bypassed.
Serial Clock Input. Clocks data at SDATA into the internal register.
Serial Data Input. Input data is clocked to the internal register to
enable/disable individual outputs. This provides flexibility in power
management.
VDDC
VDDC
VDDC
29
FB_OUT
VDDC
O
25
SYNC
VDDC
O
42, 43
SELA(1,0)
I
PU
40, 41
SELB(1,0)
I
PU
19, 20
SELC(1,0)
I
PU
5, 26, 27
FB_SEL(2:0)
I
PU
52
VCO_SEL
I
PU
31
FB_IN
I
PU
6
PLL_EN
I
PU
7
REF_SEL
I
PU
8
TCLK_SEL
I
PU
2
MR#/OE
I
PU
14
INV_CLK
I
PU
3
SCLK
I
PU
4
SDATA
I
PU
17, 22, 28,
33,37, 45, 49
13
1, 15, 24, 30,
35, 39, 47, 51
A bypass capacitor (0.1
μ
F) should be placed as close as possible to each positive power pin (<0.2”). If these bypass
capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of
the traces.
VDDC
3.3V Power Supply for Output Clock Buffers.
VDD
3.3V Supply for PLL
VSS
Common Ground
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Z9974CA | DIODE TVS 16V 500W BI-DIR |
| ZAD1025 | DIODE TVS 5.0V 500W UNI-DIR |
| ZAD1030 | Converter IC |
| ZAD1202 | SCR Thyristor; Thyristor Type:Standard Gate; Peak Repetitive Off-State Voltage, Vdrm:1000V; On-State RMS Current, IT(rms):8A; Peak Non Repetitive Surge Current, Itsm:100A; Gate Trigger Current Max, Igt:15uA RoHS Compliant: Yes |
| ZAD2736-2BU | DIODE TVS 180V 400W BIDIR 5% SMA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Z9974 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V, 125-MHz, Multi-Output Zero Delay Buffer |
| Z9974CA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FOURTEEN DISTRIBUTED-OUTPUT CLOCK DRIVER|TQFP|52PIN|PLASTIC |
| Z9975 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V, 150MHz, Multi-Output Zero Delay Buffer |
| Z9975CA | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V, 150MHz, Multi-Output Zero Delay Buffer |
| Z99SC61235 | 制造商:MINI CIRCU 功能描述:NEW |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。