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參數(shù)資料
| 型號： | Z86C90 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | ROMLESS CMOS Z8 8-BIT MICROCONTROLLER |
| 中文描述： | 無ROM的CMOS Z8 8位微控制器 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 96K |
| 代理商： | Z86C90 |
9
AC CHARACTERISTICS
External I/O or Memory Read and Write Timing Table
No Symbol
Parameter
V
Note[3]
T
= 0
°
C to +70
°
C
8 MHz
Min
Max
T
= -40
°
C to +105
°
C
8 MHz
Min
Max
Units
Notes
12 MHz
Min
12 MHz
Min
Max
Max
1
TdA(AS)
Address Valid to
/AS Rising Delay
/AS Rising to Address
Float Delay
3.3
5.0
3.3
5.0
55
55
70
70
35
35
45
45
55
55
70
70
35
35
45
45
ns
ns
ns
ns
[2]
2
TdAS(A)
[2]
3
TdAS(DR)
/AS Rising to Read
Data Required Valid
/AS Low Width
3.3
5.0
3.3
5.0
400
400
250
250
400
400
250
250
ns
ns
ns
ns
[1,2]
4
TwAS
80
80
55
55
80
80
55
55
[2]
5
Td
Address Float to
/DS Falling
/DS (Read) Low Width
3.3
5.0
3.3
5.0
0
0
300
300
0
0
200
200
0
0
300
300
0
0
200
200
ns
ns
ns
ns
6
TwDSR
[1,2]
7
TwDSW
/DS (Write) Low Width 3.3
165
165
110
110
165
165
110
110
ns
ns
ns
ns
[1,2]
5.0
3.3
5.0
8
TdDSR(DR)
/DS Falling to Read
Data Required Valid
260
260
150
160
260
260
150
160
[1,2]
9
ThDR(DS)
Read Data to
/DS Rising Hold Time
/DS Rising to Address
Active Delay
3.3
5.0
3.3
5.0
0
0
85
95
0
0
45
55
0
0
85
95
0
0
45
55
ns
ns
ns
ns
[2]
10
TdDS(A)
[2]
11
TdDS(AS)
/DS Rising to /AS
Falling Delay
R//W Valid to /AS
Rising Delay
3.3
5.0
3.3
5.0
60
70
70
70
30
45
45
45
60
70
70
70
30
45
45
45
ns
ns
ns
ns
[2]
12
TdR/W(AS)
[2]
13
TdDS(R/W)
/DS Rising to
R//W Not Valid
3.3
5.0
70
70
80
80
45
45
55
55
70
70
80
80
45
45
55
55
ns
ns
ns
ns
[2]
14
TdDW(DSW) Write Data Valid to /DS 3.3
Falling (Write) Delay
[2]
5.0
15
TdDS(DW)
/DS Rising to Write
Data Not Valid Delay
Address Valid to Read
Data Required Valid
3.3
5.0
3.3
5.0
70
80
45
55
70
80
45
55
ns
ns
ns
ns
[2]
16
TdA(DR)
475
475
310
310
475
475
310
310
[1,2]
17
TdAS(DS)
/AS Rising to
/DS Falling Delay
Data Input Setup to
/DS Rising
/DM Valid to /AS
Falling Delay
3.3
5.0
0.0
5.0
3.3
5.0
100
100
115
75
55
55
65
65
115
75
35
35
100
100
115
75
55
55
65
65
115
75
35
35
ns
ns
ns
ns
ns
ns
[2]
18
TdDI(DS)
[1,2]
19
TdDM(AS)
[2]
Notes:
[1]
[2]
[3]
When using extended memory timing add 2 TpC.
Timing numbers given are for minimum TpC.
5.0V
±
0.5V, 3.3V
±
0.3V.
Standard Test Load
All timing references use 0.9 V
CC
for a logic 1 and 0.1 V
CC
for a logic 0.
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