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| 型號(hào)： | Z8612912SSC |
| 廠商： | ZILOG INC |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | CAP 0.1UF 100V 10% X7R AXIAL TR-14 |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO18 |
| 封裝： | PLASTIC, SOIC-18 |
| 文件頁(yè)數(shù)： | 21/50頁(yè) |
| 文件大?。?/td> | 927K |
| 代理商： | Z8612912SSC |
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Z86129/130/131
NTSC Line 21 Decoder
P R E L I M I N A R Y
DS96TEL0200
21
1
The master's sequence for reading two
data bytes
(total
of three bytes including SSB) from the Z86129/130/131 is
given as:
Start-Slave Address Read/Slave ACK-SS Byte/Master
ACK-Byte (slave)/Master ACK-Byte (slave)/Master NACK-
Stop
Clock and Data Transitions.
The SCK and SDA bus lines
are normally pulled High with a resistor. Data on the SDA
bus may only change during SCK Low time periods. Data
changes during SCK High periods will indicate a start or
stop condition as defined in Table 7.
Start Condition.
A High-to-Low transition of SDA with
SCK High is a start condition which must precede any
other command.
Stop Condition.
A Low-to-High transition of SDA with
SCK High is a stop condition which terminates all
communications.
Acknowledge.
All address and data words are serially
transmitted to and from the Z86129/130/131 in eight bit
words. A ninth bit time is used for the acknowledge. The
acknowledging device does so by pulling the SDA bus Low
during the ninth bit. A Not Acknowledge (NACK) is given
by SDA=High during the ninth clock time.
Figure 10. I
2
C Bus READ (Command)
STRT
STOP
SLAVE
ADDR
SERIAL
STATUS
(READ=29h)
(SSB)
NACK
STRT
STOP
SLAVE
ADDR
SERIAL
STATUS
(READ=29h)
(SSB)
READ
DATA1
NACK
STRT
STOP
SLAVE
ADDR
SERIAL
STATUS
(READ=29h)
(SSB)
READ
DATA1
READ
DATA2
NACK
I2C-One Byte Write (Status Only)
I2C-Two Byte Read (Status & Data1)
I2C-Three Byte Read (Status, Data1, & Data2)
Note:
In all I
2
C Read operations defined herein, the last byte read
from the Z86129/130/131 must be acknowledged by the master
with a NACK (Not ACKnowledge).
Figure 11. I
2
C Serial Timing
SDA (IN)
SCK
t
SU.STA
SDA (OUT)
t
HD.STA
t
AA
t
F
t
High
t
Low
t
HD.DAT
t
SU.DAT
t
DH
t
R
t
SU.STO
t
BUF
Table 7. I
2
C Serial Timing Min/max
Symbol
f
SCK
t
LOW
t
High
t
R
t
F
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
SU.STO
t
DH
t
I
Parameter
Clock Frequency
Clock Pulse Width Low
Clock Pulse Width High
SDA and SCL Rise Time
SDA and SCL Fall Time
Clock Low to Data Out Valid
Bus Free Time
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Stop Set-up Time
Data Out Hold Time
Input Filter Time Constant
Min
Max
100
–
–
1.0
300
3.5
–
–
–
–
–
–
–
100
Units
kHz
μ
s
μ
s
μ
s
ns
μ
s
μ
s
μ
s
μ
s
μ
s
ns
μ
s
ns
ns
4.7
4.0
–
–
0.1
4.7
4.0
4.7
0
250
4.7
100
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Z8612912SSC00TR | 功能描述:IC CLOSED CAPTION DECODER 18SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類(lèi)型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱(chēng):Q4645799 |
| Z8612912SSG | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 CC DECODER RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| Z8612912SSG00TR | 制造商:Zilog Inc 功能描述:Z86129 Series 5 V Surface Mount NTSC Line 21 Decoder - SOIC-18 |
| Z8613 | 制造商:ZILOG 制造商全稱(chēng):ZILOG 功能描述:Full-duplex UART and two programmable 8-bit counter/timers, each with a 6-bit |
| Z86130 | 制造商:ZILOG 制造商全稱(chēng):ZILOG 功能描述:NTSC LINE 21 DECIDER |
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