參數(shù)資料
型號(hào): XRT91L31IQ-F
廠商: Exar Corporation
文件頁(yè)數(shù): 22/41頁(yè)
文件大?。?/td> 0K
描述: IC TXRX SONET/SDH 8BIT 64QFP
標(biāo)準(zhǔn)包裝: 1
類型: 收發(fā)器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH
輸入: LVCMOS,LVPECL,LVTTL
輸出: LVCMOS,LVPECL,LVTTL
電路數(shù): 1
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-FQFP
供應(yīng)商設(shè)備封裝: 64-PQFP(10x10)
包裝: 托盤
其它名稱: 1016-1361
XRT91L31
29
REV. 1.0.2
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
3.7
Loop Timing and Clock Control
Two types of loop timing are possible in the XRT91L31.
In the internal loop timing mode, loop timing is controlled by the LOOPTIME pin. This mode is selected by
asserting the LOOPTIME signal to a high level. When the loop timing mode is activated, the CMU synthesized
hi-speed reference clock input to the Retimer is replaced with the hi-speed internally recovered receive clock
coming from the CDR. Under this condition both the transmit and receive sections are synchronized to the
internally recovered receive clock. Loop time mode directly locks the Retimer to the recovered receive clock.
In external loop timing mode, the XRT91L31 allows the user the flexibility of using an externally recovered
receive clock for retiming the high speed serial data. First, the CDRDIS input pin should be set high. By doing
so, the internal CDR is disabled and bypassed and the XRT91L31 will sample the incoming high speed serial
data on RXIP/N with the externally recovered receive clock connected to the XRXCLKIP/N inputs. In this state,
the receive clock de-jittering and recovery is done externally and fed thru XRXCLKIP/N and the XRT91L31 will
sample RXIP/N on the rising edge of XRXCLKIP/N. Secondly, the LOOPTIME pin must also be set high in
order to select the externally recovered receive clock on XRXCLKIP/N as the reference clock source for the
transmit serial data output stream TXOP/N.
Table 17 provides configuration for selecting the loop timing and clock recovery modes. The use of the on-chip
CDR or an external recovered clock in loop timing applications is shown in Figure 16.
TABLE 17: LOOP TIMING AND CLOCK RECOVERY CONFIGURATIONS
CDRDIS
LOOPTIME
TRANSMIT CLOCK SOURCE
RECEIVE CLOCK SOURCE
0
Clock Multiplier Unit
CDR Enabled.
Clock and Data recovery by internal CDR
0
1
Internal CDR
CDR Enabled.
Clock and Data recovery by internal CDR
1
0
Clock Multiplier Unit
CDR Disabled.
Externally recovered Receive Clock from
XRXCLKIP/N
622.08/155.52 Mbps data on RXIP/N sam-
pled at rising edge of XRXCLKIP/N
1
External CDR thru XRXCLKIP/N
CDR Disabled.
Externally recovered Receive Clock from
XRXCLKIP/N
622.08/155.52 Mbps data on RXIP/N sam-
pled at rising edge of XRXCLKIP/N
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT91L31IQ-F 制造商:Exar Corporation 功能描述:SONET Transceiver IC
XRT91L31IQTR 功能描述:總線收發(fā)器 SONET/SDH, FULL DPLX 3.3V I/O, LOS, CMU RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L31IQTR-F 功能描述:總線收發(fā)器 SONET/SDH, FULL DPLX 3.3V I/O, LOS, CMU RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L32 制造商:EXAR 制造商全稱:EXAR 功能描述:STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L32ES 功能描述:LIN 收發(fā)器 SONET SDH 8 bit TRANCEIVER RoHS:否 制造商:NXP Semiconductors 工作電源電壓: 電源電流: 最大工作溫度: 封裝 / 箱體:SO-8