參數(shù)資料
型號(hào): XRT83SL314IB
廠(chǎng)商: Exar Corporation
文件頁(yè)數(shù): 83/83頁(yè)
文件大小: 0K
描述: IC LIU SH T1/E1/J1 14CH 304TBGA
標(biāo)準(zhǔn)包裝: 27
類(lèi)型: 線(xiàn)路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 14/14
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 304-LBGA
供應(yīng)商設(shè)備封裝: 304-TBGA(31x31)
包裝: 托盤(pán)
xr
XRT83SL314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
6
RLOS
AB1
O
Receive Loss of Signal (Global Pin for All 14-Channels)
When a receive loss of signal occurs for any one of the 14-channels according
to ITU-T G.775, the RLOS pin will go "High" for a minimum of one RCLK cycle.
RLOS will remain "High" until the loss of signal condition clears.
See the
Receive Loss of Signal section of this datasheet for more details.
NOTE: This pin is for redundancy applications to initiate an automatic switch to
the backup card. For individual channel RLOS, see the register map.
RCLK13
RCLK12
RCLK11
RCLK10
RCLK9
RCLK8
RCLK7
RCLK6
RCLK5
RCLK4
RCLK3
RCLK2
RCLK1
RCLK0
AB14
Y22
R22
P22
G22
F22
B14
B9
F2
G2
P2
R2
AA2
AA9
O
Receive Clock Output
RCLK is the recovered clock from the incoming data stream. If the incoming
signal is absent or RxON is pulled "Low", RCLK maintains its timing by using
an internal master clock as its reference. RPOS/RNEG data can be updated
on either edge of RCLK selected by RCLKE in the appropriate global register.
NOTE: RCLKE is a global setting that applies to all 14 channels.
RPOS13
RPOS12
RPOS11
RPOS10
RPOS9
RPOS8
RPOS7
RPOS6
RPOS5
RPOS4
RPOS3
RPOS2
RPOS1
RPOS0
Y14
W20
P20
N20
H20
G20
D14
D10
G4
H4
N4
P4
W4
Y10
O
RPOS/RDATA Output
Receive digital output pin. In dual rail mode, this pin is the receive positive
data output. In single rail mode, this pin is the receive non-return to zero (NRZ)
data output.
RECEIVER SECTION
NAME
PIN
TYPE
DESCRIPTION
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