REV. 1.0.7 6.4 Intel Mode Programmed I/O Access (Asynchronous) If " />
參數(shù)資料
型號(hào)： XRT83SH38IB-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 46/78頁(yè)
文件大小： 0K
描述： IC LIU SH T1/E1/J1 8CH 225BGA
標(biāo)準(zhǔn)包裝： 84
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 8/8
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 225-BGA
供應(yīng)商設(shè)備封裝： 225-BGA（19x19）
包裝： 托盤
XRT83SH38
47
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.7
6.4
Intel Mode Programmed I/O Access (Asynchronous)
If the LIU is interfaced to an Intel type P, then it should be configured to operate in the Intel mode. Intel type
Read and Write operations are described below.
Intel Mode Read Cycle
Whenever an Intel-type P wishes to read the contents of a register, it should do the following.
1.
Place the address of the target register on the address bus input pins ADDR[7:0].
2.
While the P is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the LIU, by toggling it "Low". This action enables further communication between the
P and the LIU microprocessor interface block.
3.
Toggle the ALE input pin "High". This step enables the address bus input drivers, within the microproces-
sor interface block of the LIU.
4.
The P should then toggle the ALE pin "Low". This step causes the LIU to latch the contents of the address
bus into its internal circuitry. At this point, the address of the register has now been selected.
5.
Next, the P should indicate that this current bus cycle is a Read operation by toggling the RD input pin
"Low". This action also enables the bi-directional data bus output drivers of the LIU.
6.
After the P toggles the Read signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this
in order to inform the P that the data is available to be read by the P, and that it is ready for the next com-
mand.
7.
After the P detects the RDY signal and has read the data, it can terminate the Read Cycle by toggling the
RD input pin "High".
NOTE: ALE can be tied “High” if this signal is not available.
The Intel Mode Write Cycle
Whenever an Intel type P wishes to write a byte or word of data into a register within the LIU, it should do the
following.
1.
Place the address of the target register on the address bus input pins ADDR[7:0].
2.
While the P is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the LIU, by toggling it "Low". This action enables further communication between the
P and the LIU microprocessor interface block.
3.
Toggle the ALE input pin "High". This step enables the address bus input drivers, within the microproces-
sor interface block of the LIU.
4.
The P should then toggle the ALE pin "Low". This step causes the LIU to latch the contents of the address
bus into its internal circuitry. At this point, the address of the register has now been selected.
5.
The P should then place the byte or word that it intends to write into the target register, on the bi-direc-
tional data bus DATA[7:0].
6.
Next, the P should indicate that this current bus cycle is a Write operation by toggling the WR input pin
"Low". This action also enables the bi-directional data bus input drivers of the LIU.
7.
After the P toggles the Write signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this
in order to inform the P that the data has been written into the internal register location, and that it is ready
for the next command.
NOTE: ALE can be tied “High” if this signal is not available.
The Intel Read and Write timing diagram is shown in Figure 36. The timing specifications are shown in
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