參數資料
| 型號： | XRT8020IL-F |
| 廠商： | Exar Corporation |
| 文件頁數： | 10/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK MULTIPLR LVDS 16QFN |
| 標準包裝： | 490 |
| 類型： | 時鐘/頻率倍增器 |
| PLL： | 是 |
| 主要目的： | 以太網，SONET/SDH |
| 輸入： | 晶體 |
| 輸出： | LVDS |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 675MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VQFN 裸露焊盤 |
| 供應商設備封裝： | 16-QFN-EP（4x4） |
| 包裝： | 散裝 |
XRT8020
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
REV. 1.0.2
6
The XRT8020 synthesizer jitter performance is optimized by calibration of its Voltage Controlled Oscillator
(VCO) upon initial power application. This power ON calibration procedure is automatic and completely trans-
parent to the user. It is initiated automatically upon first application of VDD. In order to bring the center fre-
quency of the VCO close to the desired output frequency, the VCO bias current is adjusted via a current DAC
at initial power application. The center frequency of VCO is checked against input reference frequency and cal-
ibrated internally to the desired output frequency value. These bias voltage trim bits are then held in latches for
as long as the VDD is held above 2.7V (minimum specified operational value of VDD). The user should note
following important facts about this calibration procedure for proper operation of the XRT8020:
For proper operation of the chip and to achieve lowest jitter, the user should follow layout guidelines as
described in the User Guide.
An input crystal of appropriate frequency should be connected at XTAL1 and XTAL2 pins before power is
applied to the chip.
All VDD pins should be tied to 3.3V ±10% simultaneously.
The power supply should turn on without bouncing below 2.0V smoothly to its specified value in no more
than 50msec.
The calibration takes place during VDD ramp up between 2.6V to 3V values. Once the VDD reaches and
maintains 3.0V, the chip retains the calibrated VCO bias voltages in internal latches for proper operation.
To change a widely different value of crystal or input reference frequency, it is recommended to power
down the chip by bringing VDD to 0V and restarting after the change in frequency has occurred.
2.0
CRYSTAL SELECTION
It is recommended that a Fundamental Mode Crystal be used as the timing reference of the XRT8020. The fol-
lowing part has been qualified by EXAR:
CITIZEN Quartz Crystals
20 MHz : HCM49-20.000MABJT
40 MHz : HCM49-40.000MABJT
3.0
DATA AND PLOTS
All plots were recorded using the following parameters and test setup:
VDD = 3.3 V
2” 100
Differential Transmission Lines (from LVDS outputs to receiver inputs)
Fundamental Mode Crystal of 20 MHz
Vref = 1.5 V (PECL Receiver)
FIGURE 4. INPUT REFERENCED JITTER CONNECTION DIAGRAM
XRT8020
Channel 1
Channel 2
MAX9111ESA
Tektronix
TDS7404
Tektronix
P6330 Differential Probe
Tektronix
P6245 TDS 500/600
Outp
Outn
20.0Mhz
Crystal
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