參數(shù)資料
型號: XRT75L00IV
廠商: Exar Corporation
文件頁數(shù): 39/50頁
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 SGL 52TQFP
標準包裝: 96
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 52-LQFP
供應商設備封裝: 52-TQFP(10x10)
包裝: 托盤
XRT75L00
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.2
42
0x06
R/W
D0
SR/DR
Writing a “1” to this bit configures the Receiver and
Transmitter into Single-Rail (NRZ) mode.
0
D1
STS-1/DS3
Writing a “1” to this bit configures the channel 0 into
STS-1 mode.
NOTE: This bit field is ignored if the chip is configured
to operate in E3 mode.
0
D2
E3
Writing a “1” to this bit configures the chip in E3
mode.
0
D3
LLB
Writing a “1” to this bit configures the chip in Local
Loopback mode.
0
D4
RLB
Writing a “1” to this bit configures the chip in Remote
Loopback mode.
0
D5
PRBSEN
Writing a “1” to this bit enables the PRBS generator/
detector.PRBS generator generate and detect either
215-1 (DS3 or STS-1) or 223-1 (for E3).
The pattern generated and detected are unframed
pattern.
0
0x07
R/W
D0
JA0
This bit along with JA1 bit configures the Jitter Attenu-
ator as shown in the table below.
0
D1
JATx/Rx
Writing a “1” to this bit selects the Jitter Attenuator in
the Transmit Path. A “0” selects in the Receive Path.
0
D2
JA1
This bit along with the JA0 configures the Jitter Atten-
uator as shown in the table.
0
D3
PNTRST
Setting this bit to “1” resets the Read and Write point-
ers of the jitter attenuator FIFO.
0
TABLE 16: REGISTER MAP DESCRIPTION
ADDRESS
(HEX)
TYPE
BIT LOCATION
SYMBOL
DESCRIPTION
DEFAULT
VALUE(BIN)
RLB
0
Loopback Mode
Normal Operation
Analog Local
LLB
0
1
Remote
Digital
0
1
JA0
0
Mode
16 bit FIFO
32 bit FIFO
JA1
0
1
Disable Jitter
Attenuator
0
1
Disable Jitter
Attenuator
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