參數(shù)資料
型號(hào): XRT71D03IVTR-F
廠商: Exar Corporation
文件頁(yè)數(shù): 6/24頁(yè)
文件大小: 0K
描述: IC JITTER ATTENUATOR 3CH 64TQFP
標(biāo)準(zhǔn)包裝: 1,000
類(lèi)型: *
PLL:
輸入: 時(shí)鐘
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 3:2
差分 - 輸入:輸出: 無(wú)/無(wú)
頻率 - 最大: 44.736MHz
除法器/乘法器: 無(wú)/無(wú)
電源電壓: 3.135 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 帶卷 (TR)
XRT71D03
á
3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR
REV. 1.2.0
13
The XRT71D03 DS3/E3 Jitter Attenuator IC consists
of the following functional blocks:
The Jitter-Attenuator PLL
Timing Control Block
The 2-Channel 16/32 Bit FIFO
Serial Microprocessor Interface
1.0
JITTER ATTENUATOR PLL
1.1
BACKGROUND INFORMATION DEFINITION OF JIT-
TER
One of the most important and least understood mea-
sures of clock performance is jitter. The International
Telecommunication Union defines jitter as short term
variations of the significant instants of a digital signal
from their ideal positions in time. Jitter can occur due
to any of the following:
1) Imperfect timing recovery circuit in the system
2) Cross-talk noise
3) Inter-symbol interference/Signal Distortion
1.2
JITTER TRANSFER CHARACTERISTICS
The primary purpose of jitter transfer requirements is
to prevent performance degradations by limiting the
accumulation of jitter through the system such that it
does not exceed the network interface jitter require-
ments. Thus, it is more important that a system meet
the jitter transfer criteria for relatively high input jitter
amplitudes. The jitter transferred through the system
must be under the jitter mask for any input jitter ampli-
tude within the range as shown in Figure 7
FIGURE 6. ILLUSTRATION OF A TYPICAL CHANNEL_N OF THE XRT71D03 (CONFIGURED TO OPERATE IN THE HOST
MODE)
HOST
Reset
16/32 Bit FIFO
Microprocessor Serial
Interface
Timing Control Block /
Phase locked Loop
Write Clock
Read Clock
RRCLK_n
RRPOS_n
RRNEG_n
FL_n
RCLK_n
RPOS_n
RNEG_n
ICT
CS
SDI
SDO SClk
MClk_n
Smoothed
Clock
Jittery
Clock
RRCLKES
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