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參數(shù)資料
| 型號(hào)： | XRD98L62EVAL |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 37/37頁 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD XRD98L62 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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9
Rev. P2.00
XRD98L62
Preliminary
Serial Interface
The XRD9862 uses a three wire serial interface (LOAD,
SDI & SCLK) to access the programmable features
and controls of the chip. The serial interface uses a 16-
bit shift register. The first 6 bits shifted in are the
address bits, the next 10 bits are the data bits. The
address bits select which of the internal registers will
receive the 10 data bits. The interface will only load
data from the shift register into the register array if there
are exactly 16 rising edges of SCLK while LOAD is low.
If more or less rising edges are present, the data is
discarded. There is no checking of the address bits to
ensure a valid register is written to. If the address bits
select an undefined register, the data will be discarded.
There is a readback function (see Serial Interface
Readback section), which outputs the contents of a
selected register on pins DB[11:2] of the digital output
bus.
SCLK
SDI
LOAD
Time
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
t1
t2
t16
t15
…
t
L1
t
L2
t
SCLK
t
set
t
hold
MSB
LSB
D8
D9
A5
A4
The following is the procedure for writing to the
serial interface:
1)
Force LOAD pin low to enable shift register.
2)
Shift in 16 bits, 6 address bits (msb first),
followed by 10 data bits (msb first).
3)
Force LOAD pin high to transfer data from the
shift register to the serial interface register
array.
Note: There must be exactly 16 rising edges of
SCLK
while LOAD is low.
Figure 3. Serial Interface Timing Diagram
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