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  • 參數(shù)資料
    型號(hào): XRD9826ACUTR
    廠商: Exar Corporation
    文件頁(yè)數(shù): 19/33頁(yè)
    文件大?。?/td> 0K
    描述: IC 16B CCD/CIS SIG PROC 20SSOP
    產(chǎn)品變化通告: Leaded UART, V&I Obsolescence 11/Apr/2011
    標(biāo)準(zhǔn)包裝: 1,500
    位數(shù): 16
    通道數(shù): 3
    電壓 - 電源,模擬: 3V,5V
    電壓 - 電源,數(shù)字: 3V,5V
    封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
    供應(yīng)商設(shè)備封裝: 20-SSOP
    包裝: 帶卷 (TR)
    XRD9826
    26
    Rev. 1.10
    Mode 2. DC Coupled
    Typical CCDs have outputs with black references.
    Therefore, DC Coupled is not recommended for CCD
    applications.
    Offset Control DAC
    The offset DAC is controlled by 8 bits. The offset range
    is 800 mV ranging from -200 mV to +600 mV (when DB5
    is set to 0) and -400 mV to +400 mV (when DB5 is set
    to 1). Therefore, the resolution of the 8-Bit offset DAC
    is 3.14 mV. However, the XRD9826 has +/- 100 mV
    reserved for internal offsets. Therefore, the effective
    range for adjusting for CIS offsets or black reference is
    600 mV. The offset adjustment is used primarily to
    correct for the difference between the black level of the
    image sensor and the bottom ladder reference voltage
    (VRB) of the ADC. By adjusting the black level to
    correspond to VRB, the entire range of the ADC can be
    used.
    If the offset of the CIS output is greater than 500 mV an
    external reference can be applied to VDCEXT. The
    external reference can be used to adjust for large
    offsets only when the internal mode is configured
    through the serial port.
    Since the offset DAC adjustment is done before the
    gain stage, it is gain-dependent. For example, if the
    gain needs to be changed between lines (red to blue,
    etc.), the offset is calibrated before the signal passes
    through the PGA.
    PGA (Programmable Gain Amplifier) DAC
    The gain of the input waveform is controlled by a 6-Bit
    PGA. The PGA is used along with the offset DAC for
    the purpose of using the entire range of the ADC. The
    PGA has a linear gain from 1 to 10. Figure 19 is a plot
    of the transfer curve for the PGA gain.
    PGA GAIN TRANSFER CURVE
    GAIN 1 - 10
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    0
    1020
    3040
    50
    60
    CODE
    GAIN
    Figure 20. Transfer Curve for the 6-Bit PGA
    After the signal is level shifted to correspond with the
    bottom ladder reference voltage, the system can be
    calibrated such that a white video pixel can represent
    the top ladder reference voltage to the ADC. This allows
    for a full scale conversion maximizing the resolution of
    the ADC.
    Analog to Digital Converter
    The ADC is a 16-bit, 10 MSPS analog-to-digital con-
    verter for high speed and high accuracy. The ADC uses
    a subranging architecture to maintain low power con-
    sumption at high conversion rates. The output of the
    ADC is on an 8-bit databus. The 8-bit databus supports
    8x8 output data. ADCCLK samples the input on its
    falling edge. After the input is sampled, the MSB (8
    upper bits) is latched to the output drivers. On the rising
    edge of the ADCCLK, the LSB (8 lower bits) is latched
    to the output drivers.
    The output needs to be
    demultiplexed with external circuitry or a digital ASIC.
    There is an 8 clock cycle latency (Config 00, 11) or 6
    pixel count latency (Config 01, 10) for the analog-to-
    digital converter.
    The V
    RT and VRB reference voltages for the ADC are
    generated internally, unless the external V
    RT
    is se-
    lected. In the external V
    RT mode, the VRT voltage is set
    through the VREF+ pin. This allows the user to select
    the dynamic range of the ADC.
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